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公开(公告)号：KR1019930006620B1
公开(公告)日：1993-07-21
申请号：KR1019900017910
申请日：1990-11-06
Applicant: 한국전자통신연구원
IPC: G11C11/401
CPC classification number: G11C11/404 , G11C11/4099
Abstract: The dynamic RAM removes induced memory cell noise by offsetting with a differential amplifier in the memory, a pair of reference memory cells having the same characteristics are each consisted of one bit memory cell to read and write, and this results in the same noise effects to both the reference memory cells. The equally distributed noise can be offset by the differential amplifier, and the DRAM misoperation can be protected by reducing external noise or internal array noise.
Abstract translation: 动态RAM通过与存储器中的差分放大器抵消来消除感应的存储器单元噪声，具有相同特性的一对参考存储器单元分别由读取和写入的一位存储器单元组成，并且这导致相同的噪声效应 两个参考存储单元。 均匀分布的噪声可以由差分放大器抵消，并且可以通过减少外部噪声或内部阵列噪声来保护DRAM误操作。
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公开(公告)号：KR1019930004985B1
公开(公告)日：1993-06-11
申请号：KR1019900004605
申请日：1990-04-03
Applicant: 한국전자통신연구원
IPC: H01L27/108
Abstract: The stack-structured DRAM consists of source and drain region (10) for transistor between gate structure (6,7,7a) formed on P-type silicon substrate (1); corresponding contact parts for storage electrodes formed on (10); 1st storage electrode (13,15,18) having polysilicon sidewall spacer (18) connecting with top and bottom polysilicon films (13,15) separated by silicon oxide (14) ; 2nd storage electrodes (20,22,24) having polysilicon sidewall spacer (24) connecting with top and bottom polysilicon films (20,22) separated by silicon oxide (14); and plate region (25) formed by impurity-doped polysilicon between the first and second storage electrodes. The 2nd electrode partially overlaps with polysilicons (13,15).
Abstract translation: 堆叠结构的DRAM由在P型硅衬底（1）上形成的栅极结构（6,7,7a）之间的晶体管的源极和漏极区（10）组成; 在（10）上形成的用于存储电极的对应的接触部分; 具有与由氧化硅（14）分开的顶部和底部多晶硅膜（13,15）连接的多晶硅侧壁间隔物（18）的第一存储电极（13,15,18）; 具有与由氧化硅（14）分开的顶部和底部多晶硅膜（20,22）连接的多晶硅侧壁间隔物（24）的第二存储电极（20,22,24）; 以及由所述第一和第二存储电极之间的杂质掺杂多晶硅形成的板区域（25）。 第二电极与多晶硅部分重叠（13,15）。
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Patent Agency Ranking
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公开(公告)号：KR1019920004370B1
公开(公告)日：1992-06-04
申请号：KR1019890017061
申请日：1989-11-23
Applicant: 한국전자통신연구원
IPC: H01L27/108
Abstract: The DRAM cell is manufactured by defining an active region on a P- silicon substrate (1), forming a transistor to form a polyside layer (10) for bit line, applying a silicon nitride film (11) of 50-100 nm as an etch-stop layer, defining a contact region (15) between a source and a storage electrode of the transistor to form a grid- shaped oxide film (16) with the minimum line width, depositing a polysilicon side wall electrode (18) for charge storage at 50-100 nm thickness to apply an oxide film to dry-etch the oxide film to form a side wall spacer (19) of oxide film, depositing a second polysilicon side wall electrode (20) to apply a photosensitive film (22) to etch-back the polysilicon to form a double polysilicon side wall, and doping polysilicon side wall electrodes (18,20) to form a dielectric film for capacitor to define a plate electrode (23), thereby incrasing the storage capacitor
Abstract translation: 通过在P-硅衬底（1）上限定有源区，形成晶体管以形成用于位线的多边层（10）来制造DRAM单元，施加50-100nm的氮化硅膜（11）作为 蚀刻停止层，限定晶体管的源极和存储电极之间的接触区域（15），以形成具有最小线宽度的栅格氧化膜（16），沉积用于充电的多晶硅侧壁电极（18） 以50-100nm的厚度存储以施加氧化膜以干蚀刻氧化膜以形成氧化膜的侧壁间隔物（19），沉积第二多晶硅侧壁电极（20）以施加感光膜（22） 以蚀刻多晶硅以形成双多晶硅侧壁，并掺杂多晶硅侧壁电极（18,20）以形成用于电容器的电介质膜以限定平板电极（23），从而增加存储电容器
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公开(公告)号：KR1019920004368B1
公开(公告)日：1992-06-04
申请号：KR1019890012747
申请日：1989-09-04
Applicant: 한국전자통신연구원
IPC: H01L27/108
CPC classification number: H01L27/10861 , H01L28/40
Abstract: The method for increasing the area of a storage capacitor comprises the steps of etching a substrate (33) having a P-well to form a first trench to form a silicon nitride film (35) thereon, forming an oxide film (36) and a silicon nitride film (37) to etch the substrate to form a second trench to form a side wall field oxide film (4) and a masking silicon oxide film (38) thereon, etching the substrate to form a third trench to dope PSG materials onto the substrate to form a substrate electrode, wet-etching the masking film (38) to form first and second capacitor dielectric regions (43a)(43b), doping a polysilicon layer (44) to etch the substrate to remove the polysilicon layer (44) to etch the substrate to remove the polysilicon and dielectric materials from the trench, and forming a polysilicon plate electrode. The method increases the area of storage capacitor.
Abstract translation: 用于增加存储电容器的面积的方法包括以下步骤：蚀刻具有P阱的衬底（33）以形成第一沟槽以在其上形成氮化硅膜（35），形成氧化物膜（36）和 氮化硅膜（37），以蚀刻所述衬底以形成第二沟槽以在其上形成侧壁场氧化膜（4）和掩模氧化硅膜（38），蚀刻所述衬底以形成第三沟槽以将PSG材料涂覆到 衬底以形成衬底电极，湿蚀刻掩模膜（38）以形成第一和第二电容器介电区域（43a）（43b），掺杂多晶硅层（44）以蚀刻衬底以去除多晶硅层（44 ）以蚀刻衬底以从沟槽去除多晶硅和电介质材料，以及形成多晶硅板电极。 该方法增加了存储电容的面积。
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