公开(公告)号：WO1996016479A1

公开(公告)日：1996-05-30

申请号：PCT/US1995013189

申请日：1995-10-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  SHARPE-GEISLER, Bradley, A. ,  FONTANA, Fabiano

IPC: H03K19/177

CPC classification number: H03K19/17708 ,  H03K19/018521

Abstract: A high density programmable logic device (PLD) having sense amplifiers and OR gates configured to increase operation speed and reduce transistor count from previous circuits as well as to provide a selectable power down mode on a macrocell-by-macrocell basis. The sense amplifiers include a single cascode in the data path connecting a product term of the OR gates. The OR gates utilize a plurality of source follower transistors followed by pass gates to provide logic allocation enabling the sense amplifier outputs to be reduced from the 0.0 V - 5.0 V CMOS rails to increase switching speed while reducing overall transistor count. Amplifying inverters normally provided in the sense amplifiers to provide the CMOS rail-to-rail switching and which would require complex feedback for providing power down on a macrocell-by-macrocell basis are moved forward into OR output circuits. Power down on a macrocell-by-macrocell basis is provided by selectively sizing the amplifying inverters in the OR output circuits.

Abstract translation: 具有读出放大器和OR门的高密度可编程逻辑器件（PLD）被配置为增加操作速度并减少来自先前电路的晶体管数量，以及在逐个宏单元的基础上提供可选择的掉电模式。 读出放大器包括连接OR门产品项的数据路径中的单个共源共栅。 OR门使用多个源极跟随器晶体管，随后是通过栅极，以提供逻辑分配，使得读出放大器输出能够从0.0V-5.0V CMOS轨道减小，从而提高开关速度，同时降低总体晶体管数量。 通常在读出放大器中提供的放大反相器，以提供CMOS轨到轨开关，并且这将需要复杂的反馈以便在宏单元逐宏基础上提供掉电向前进入OR输出电路。 通过在OR输出电路中选择性地调整放大逆变器来提供基于宏小区的宏单元的功率下降。

公开(公告)号：WO1996016436A1

公开(公告)日：1996-05-30

申请号：PCT/US1995013919

申请日：1995-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  AVANZINO, Steven, C. ,  WOO, Christy, Mei-Chu ,  SCHONAUER, Diana, M. ,  BURKE, Peter, Austin

IPC: H01L21/3105

CPC classification number: H01L21/3212 ,  H01L21/321

Abstract: A tungsten chemical-mechanical polishing slurry formulated from small median diameter abrasive particles having a very tight diameter variation and by thoroughly premixing the abrasive with a surfactant suspension agent before combining the oxidizer.

Abstract translation: 由具有非常紧密直径变化的小中值粒度磨料颗粒配制的钨化学机械抛光浆料，以及在组合氧化剂之前通过将表面活性剂悬浮剂彻底预混合磨料。

公开(公告)号：WO1989011688A1

公开(公告)日：1989-11-30

申请号：PCT/US1989002112

申请日：1989-05-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHAN, David, A.

IPC: G05B19/18

CPC classification number: G06F9/30061 ,  G05B19/042

Abstract: A user programmable motor control (PMC) for controlling a brushless D.C. motor is disclosed. In the PMC, an instructive program consisting of opcodes is inputted to a Micro Sequencer (1) which initiates and sequences the execution of the user's instruction. The user also inputs to Control Block (6) a desired motor speed and direction. The Control Block (6) generates a pulse width control value (PWC) to a PWM Generator (8). The PWM Generator (8) utilizes the PWC value to generate timing pulses, and through Programmalbe Commutation Logic/Driver Enable Logic (11), to control the motor speed. The motor performance information (15, 16) is fed back to user from Control Block (6). A Dead time Generator (18) sets the dead time internal (19) to insure that commutation switch overlap does not occur. The use of opcodes and the associated circuitry enables the PMC to perform various polling, branching and waiting logic to occur within one machine cycle.

Abstract translation: 公开了一种用于控制无刷直流电动机的用户可编程电动机控制（PMC）。 在PMC中，将由操作码组成的指导程序输入到微定序器（1），该定序器启动和排序用户指令的执行。 用户还向控制块（6）输入所需的电机速度和方向。 控制块（6）产生到PWM发生器（8）的脉冲宽度控制值（PWC）。 PWM发生器（8）利用PWC值产生定时脉冲，并通过Programmalbe换向逻辑/驱动使能逻辑（11）来控制电机转速。 电机性能信息（15,16）从控制块（6）反馈给用户。 死时间发生器（18）设置内部死区时间（19），以确保换相开关重叠不发生。 操作码和相关电路的使用使得PMC能够在一个机器周期内执行各种轮询，分支和等待逻辑。

公开(公告)号：WO1988002121A1

公开(公告)日：1988-03-24

申请号：PCT/US1987002371

申请日：1987-09-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  LUNDERIUS, Erik ,  SZETO, Simon ,  JOHANSSON, Jan

IPC: G01R19/00

CPC classification number: G01R19/16528 ,  H02J13/0017 ,  Y02E60/7807 ,  Y04S40/12 ,  Y10T307/826 ,  Y10T307/832

Abstract: A power controller for supplying separately a regulated power soux8e to a plurality of "S" (S0, S1, S2, S3) lines and for monitoring line-status conditions on the ''S'' line so that each "S" line is controlled independently includes an analog section (Vs, VCC, GND) for delivering power independently to each of the "S" lines and for detecting line-status conditions on "S" lines. The power controller also includes microprocessor interface section (14) for communicating with the microprocessor (11) and for controlling the analog section. The analog section is formed of a plurality of output drivers (26) for supplying individually the power to the plurality of "S" lines and line-status detector circuits (24) for sensing line-status conditions on the "S" lines to provide a set of status logic signals for each "S" line. The microprocessor interface section includes an address register (18) for storing a plurality of addresses corresponding to the line-status conditions to be monitored on the "S" lines. Decoder/multiplexers (20) are provided for selecting a particular one of the line-status conditions in response to the addresses so that the same line-status condition for all "S" line is readable simultaneously by the microprocessor. A data register (20) receives control signals from the microprocessor upon reading of the line status conditions so as to switch off independently each of the output drivers to control power to the "S" lines.

公开(公告)号：WO1986004727A1

公开(公告)日：1986-08-14

申请号：PCT/US1986000222

申请日：1986-01-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BRINER, Michael, S. ,  BILL, Colin, S. ,  SUCIU, Paul ,  RINERSON, Darrell

IPC: G11C11/40

CPC classification number: G11C16/10 ,  G11C2216/14

Abstract: A page mode write system for an E PROM array including active latches (48) for storing loaded data on bit lines (14), independent bit line grounds (28) for isolating the cells (8) in a byte (40), and program gate lines (38) in each byte (40) for tagging those bytes (40) that will undergo a charge/discharge cycle during the write cycle.

Abstract translation: 一种用于E 2 PROM阵列的页面模式写入系统，包括用于在位线（14）上存储加载的数据的有源锁存器（48），用于隔离字节（40）中的单元（8）的独立位线接地（28） ，以及每个字节（40）中的编程门线（38），用于标记在写周期期间将经历充电/放电循环的那些字节（40）。

公开(公告)号：WO1986002792A1

公开(公告)日：1986-05-09

申请号：PCT/US1984001805

申请日：1984-11-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  THOMPSON, Michael, D.

IPC: H03K19/092

CPC classification number: H03K19/01812 ,  H01L27/0207 ,  H03K19/173

Abstract: An integrated circuit device (10 in Fig. 2; 105 in Fig. 5) containing internal logic and/or memory circuitry (19; 114, 115) is provided with means to receive multiple inputs at the voltage levels of different logic families (Pi-Pi) and with means to provide multiple outputs at the voltage levels of different logic families (Pj-Pn). On-chip input translators (15, 17; 106, 108, 110, 112) receive the inputs at the level of a given logic family and translate to the level required by the internal logic and/or memory circuitry. After performance of logic and/or memory functions, on-chip output translators (16, 18; 107, 109, 111, 113) translate the otput of the internal logic and/or memory circuitry and provide external outputs at the voltage levels of different logic families. The internal logic and/or memory circuitry may be of a single logic family or may be composed of several logic families. On-chip translators may also be added between internal logic and/or memory circuitry of different families (116, 117).

Abstract translation: 包含内部逻辑和/或存储器电路（19; 114,115）的集成电路器件（图2中的10;图5中的105）被提供有用于在不同逻辑系列的电压电平 -Pi），并且具有在不同逻辑系列（Pj-Pn）的电压电平处提供多个输出的装置。 片上输入转换器（15,17; 106,108,110,112）在给定逻辑系列的电平处接收输入并转换为内部逻辑和/或存储器电路所需的电平。 在执行逻辑和/或存储器功能之后，片上输出转换器（16,18; 107,109,111,113）转换内部逻辑和/或存储器电路的输出，并以不同的电压电平提供外部输出 逻辑家庭 内部逻辑和/或存储器电路可以是单个逻辑系列，或者可以由多个逻辑系列组成。 片上翻译器也可以被添加到不同族（116,117）的内部逻辑和/或存储器电路之间。

公开(公告)号：WO1985004623A1

公开(公告)日：1985-10-24

申请号：PCT/US1985000485

申请日：1985-03-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  THOMAS, Mammen ,  KOYAMA, Linda, J.

IPC: B44C01/22

CPC classification number: H01L21/31055 ,  H01L21/76819

Abstract: Process for the planarization of an integrated circuit structure (30) by a two stage planarization process which comprises: applying over a metallization layer (40, 42, 44), having one or more openings (46, 48) therein, a layer of insulation (50') sufficiently thin to avoid formation of voids in the portion of the insulation applied in the openings in the metallization layer; smoothing the insulation layer by removing the high portions of the insulation by, for example, dry etching the insulation; applying a further layer of insulation (70) over the first insulation layer; and smoothing the further layer of insulation by removing the high portions by, for example, dry etching; whereby the resultant smoothed insulation surface will be substantially planar and substantially void-free. In a preferred embodiment, a second material, such as a photoresist material (60, 80), is coated over the insulation layer prior to the smoothing step, particularly when an anisotropic dry etching process is used, to insure that only the high portions of the insulation layer are removed in the etching step.

Abstract translation: 用于通过两级平坦化工艺对集成电路结构（30）进行平面化的方法，该方法包括：在其上具有一个或多个开口（46,48）的金属化层（40,42,44）上施加绝缘层 （50'）足够薄以避免在施加在金属化层的开口中的绝缘部分中形成空隙; 通过例如干蚀刻绝缘来去除绝缘层的高部分来平滑绝缘层; 在所述第一绝缘层上施加另外的绝缘层（70）; 以及通过例如干蚀刻去除高部分来平滑另外的绝缘层; 由此所得到的平滑绝缘表面将基本上是平面的并且基本上无空隙。 在优选实施例中，在平滑步骤之前，特别是当使用各向异性干蚀刻工艺时，在绝缘层上涂覆第二材料（例如光致抗蚀剂材料（60,80）），以确保只有高的部分 在蚀刻步骤中去除绝缘层。

公开(公告)号：WO1985004134A1

公开(公告)日：1985-09-26

申请号：PCT/US1985000355

申请日：1985-03-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  HATCHER, Owen, W.

IPC: B44C01/22

CPC classification number: H01L21/74 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A method for forming vertically spaced apart regions on an integrated circuit substrate (10). One or more recesses (28) are formed in inactive regions of the substrate, while the remaining surface of the substrate remains substantially flat. When an epitaxial layer (30) is deposited over the substrate, the recesses in the substrate cause the formation of corresponding recesses (32) in the exposed surface of the epitaxial layer. Such recesses are useful as alignment marks in properly locating the masks used in defining active regions on the surface of the epitaxial layer.

公开(公告)号：WO1985004049A1

公开(公告)日：1985-09-12

申请号：PCT/US1985000307

申请日：1985-02-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  CHEUNG, Robin, W. ,  CHAN, Hugo, W., K.

IPC: H01L29/04

CPC classification number: H01L21/76889 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76895 ,  H01L23/53271 ,  H01L29/41725 ,  H01L29/4933 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/133 ,  Y10S148/147 ,  Y10S257/904 ,  Y10S438/978 ,  H01L2924/00

Abstract: An improved integrated circuit structure characterized by enhanced step coverage and a method of making it. The structure comprises a base layer of silicon, a first oxide layer on the silicon layer, strips of poly silicon (10) having selected portions thereof reacted with a metal capable of forming a metal silicide (60) in situ on the surface of the poly silicon strips, a further oxide layer (62) over the metal silicide, and a metal layer (65) providing electrical contact to selected portions of the structure. The construction makes it possible to remove all of an intermediate oxide layer during manufacture except for an oxide layer (50a) above the poly load resistor (10d). This elimination of one oxide layer, together with the integration of the conductive metal silicide and underlying poly silicon into one layer and the rounding of the metal silicide edge with oxide spacers (58) via anisotropic etching of the intermediate oxide layer, permits better step coverage for the resulting structure .

公开(公告)号：WO1985002955A1

公开(公告)日：1985-07-04

申请号：PCT/US1984001711

申请日：1984-10-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  ALLEN, Michael

IPC: H03K19/086

CPC classification number: H03K19/0136

Abstract: An output voltage driver apparatus for an ECL circuit driving a capacitive load (CL) which comprises an emitter follower means (117) having an output emitter (118) and a reference emitter (120). The output emitter is connected to the capacitive load. A pull-down transistor means (123) is connected to the output emitter and provides a transient pull-down current for a capacitive load when the output voltage swings from a high level to a low level. A biasing means (125) is connected between the reference emitter of the emitter follower means and the pull-down transistor means so that the pull-down transistor means is biased to turn on when the voltage at the output emitter is higher than the voltage at the reference emitter by a turn-on voltage. Because the capacitive load will hold the voltage of the output emitter higher than that of the reference emitter until the capacitance of the load is discharged, the pull-down transistor means provides a transient pull-down current which speeds up the switching time of the emitter couple logic circuit.