公开(公告)号：BE1000819A3

公开(公告)日：1989-04-11

申请号：BE8701395

申请日：1987-12-04

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LENTA JORGE EDUARDO

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/362 ,  G06F13/374

Abstract: Système d'ordinateur dans lequel des unités périphériques dans un nombre supérieur au nombre des canaux DMA prévus dans le système, peuvent toutes bénéficier de l'accès DMA, certains des canaux DMA étant attribués à certaines des unités périphériques tandis que d'autres appelés canaux DMA ''programmables'', étant partagés entre le reste des unités périphériques.

公开(公告)号：GB2202975A

公开(公告)日：1988-10-05

申请号：GB8728921

申请日：1987-12-10

Applicant: IBM

Inventor： CONCILIO IAN ANTHONY ,  HAWTHORNE JEFFREY ALAN ,  HEATH CHESTER ASBURY ,  LENTA JORGE EDUARDO ,  NGUYEN LONG DUY

IPC: G06F13/30 ,  G06F13/28 ,  G06F13/36 ,  G06F13/362 ,  G06F13/374

Abstract: A computer system is coupled to peripherals having their own DMA channel arbiter and peripherals having no arbiter. A separate arbitration unit, controlled directly by the CPU, is provided to arbitrate on behalf of peripherals having no arbiter. The CPU can thus freely assign different arbitration levels to such peripherals, and can instruct the arbitration unit to simultaneously arbitrate on different arbitration levels or for two or more DMA channels.

公开(公告)号：FR2613097A1

公开(公告)日：1988-09-30

申请号：FR8716749

申请日：1987-11-27

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  JUDICE DARRYL EDMOND ,  JACKSON KEVIN MICHAEL ,  PESTONJI HOSHANG RATAN

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/78 ,  G06F13/32

Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.

公开(公告)号：FR2613095A1

公开(公告)日：1988-09-30

申请号：FR8716750

申请日：1987-11-27

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LENTA JORGE EDUARDO

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/36 ,  G06F13/362 ,  G06F13/374 ,  G06F13/10 ,  G06F9/06

Abstract: A computer system in which peripherals greater in number than the number of DMA channels provided in the system can all have DMA access. Some of the DMA channels are dedicated to certain ones of the peripherals, while others are shared by remaining ones of the peripherals. Each peripheral having DMA access has a channel priority value. When a peripheral wants DMA access, it transmits its channel priority value onto an arbitration bus. The winning channel priority value is then compared with prestored DMA channel assignment values. If the comparison is successful, the corresponding peripheral is given a DMA channel corresponding to the DMA channel assignment value with which the comparison was successful.

公开(公告)号：FR2612728A1

公开(公告)日：1988-09-23

申请号：FR8716224

申请日：1987-11-18

Applicant: IBM

Inventor： DUSI SAMUEL THOMAS ,  HEATH CHESTER ASBURY ,  MANNS KENNETH LYNN ,  NEER JAY HENRY ,  ZADEREJ VICTOR VASYL ,  ESCOBAR GERMAN ,  KIRK RICHARD DANA ,  MOORE BILLY WILLIAMS ,  SHAW RICHARD WILLIAM

IPC: G06F1/16 ,  G06F13/40 ,  G12B17/02 ,  H01R4/64 ,  H05K1/11 ,  H05K7/14 ,  H05K9/00 ,  H01R9/09

Abstract: A computer system accepting feature cards for, for example, coupling external peripheral devices includes a plurality of sockets mounted on the planar board to accept edge connectors on the cards, and slots in the main enclosure to permit coupling to external peripherals. To reduce electromagnetic radiation, the slots in the main enclosure have a depth such as to define channels, and the brackets on the cards are of U-shaped cross-section such as to fit within the channels. The channel walls are conductive, and the brackets are shaped to define spaced outward contact points which closely engage the channel walls.

公开(公告)号：DE3808168A1

公开(公告)日：1988-09-22

申请号：DE3808168

申请日：1988-03-11

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LANGGOOD JOHN KENNEDY ,  VALLI RONALD EUGENE

IPC: G06F13/14 ,  G06F1/00 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

公开(公告)号：NO880467A

公开(公告)日：1988-09-21

申请号：NO880467

申请日：1988-02-03

Applicant: IBM

Inventor： DUSI SAMUEL THOMAS ,  ESCOBAR GERMAN ,  HEATH CHESTER ASBURY ,  KIRK RICHARD DANA ,  MANNS KENNETH LYNN ,  MOORE BILLY WILLIAMS ,  NEER JAY HENRY ,  SHAW RICHARD WILLIAM

IPC: H01R4/64 ,  G06F1/16 ,  G06F13/40 ,  H05K1/11 ,  H05K7/14 ,  H05K9/00

CPC classification number: G06F13/409 ,  H05K7/1455

公开(公告)号：FR2612313A1

公开(公告)日：1988-09-16

申请号：FR8800172

申请日：1988-01-06

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  VALLI RONALD EUGENE ,  LANGGOOD JOHN KENNEDY

IPC: G06F1/00 ,  G06F1/18 ,  G06F13/14 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F12/00

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

公开(公告)号：FI880656A

公开(公告)日：1988-09-14

申请号：FI880656

申请日：1988-02-12

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  LANGGOOD JOHN KENNEDY ,  VALLI RONALD EUGENE

IPC: G06F1/00 ,  G06F13/14 ,  G06F1/18 ,  G06F1/24 ,  G06F9/44 ,  G06F9/445 ,  G06F11/22 ,  G06F12/06 ,  G06F15/177 ,  G06K17/00 ,  G06F

Abstract: A data processing system includes a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets, each adapted to receive a selected one of a plurality of different and/or similar option cards. Each card contains (or is connected to) and controls a respective peripheral device, and each card is pre-wired with an ID value corresponding to its card type. Programmable option registers on each card store parameters such as address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in socket locations in main memory, one location being assigned to each input/output socket. Each socket location is adapted to hold the parameters associated with the card inserted in its respective socket and the card ID value. That portion of main memory containing the socket locations is adapted to maintain the parameter and ID information by means of battery power when system power fails or is disconnected, i.e., a non-volatile memory portion. Subsequent power-on routines are simplified by merely transferring parameters from the memory to the card registers if the status of all the sockets has not changed since the last power-down.

公开(公告)号：IT8819826D0

公开(公告)日：1988-03-18

申请号：IT1982688

申请日：1988-03-18

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  JACKSON KEVIN MICHAEL ,  JUDICE DARRYL EDMOND ,  PESTONJI HOSHANG RATAN

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/78 ,  G06F

Abstract: A personal computer system with associated interrupt controller is preferably designed to operate with programs and respond to interrupt related commands in one mode, such as level sensitive mode, but is provided with circuitry that enables the system to convert and respond to interrupt-related software commands in another mode, such as edge sensitive (triggered) mode, the system then treating the edge mode signals just as if they were level mode signals.