公开(公告)号：GB2499314B

公开(公告)日：2014-12-17

申请号：GB201301434

申请日：2013-01-28

Applicant: IBM

Inventor： NOWAK EDWARD J ,  ANDERSON BRENT ALAN ,  BRYANT ANDRES

IPC: H01L29/78 ,  H01L29/66

Abstract: A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region.

公开(公告)号：DE102013201035A1

公开(公告)日：2013-08-08

申请号：DE102013201035

申请日：2013-01-23

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC: H01L29/78 ,  H01L21/336

Abstract: Eine Finnen-Feldeffekttransistor(FinFET)-Struktur und ein Verfahren zum Fertigen des FinFET, der eine Siliciumfinne beinhaltet, die einen Kanalbereich und Source/Drain(S/D)-Bereiche aufweist, die an jedem Ende des Kanalbereichs ausgebildet sind, wobei eine gesamte untere Fläche des Kanalbereichs mit einer oberen Fläche eines unteren Isolators in Kontakt steht und untere Flächen der S/D-Bereiche mit ersten Abschnitten von oberen Flächen einer unteren Silicium-Germanium(SiGe)-Schicht in Kontakt stehen. Die FinFET-Struktur beinhaltet außerdem extrinsische S/D-Bereiche, die mit einer oberen Fläche und beiden seitlichen Flächen jedes der S/D-Bereiche und zweiten Abschnitten von oberen Flächen der unteren SiGe-Schicht in Kontakt stehen. Die FinFET-Struktur beinhaltet des Weiteren ein Ersatz-Gate oder einen Gate-Stapel, das/der mit einem konformen Dielektrikum in Kontakt steht, das über einer oberen Fläche und beiden seitlichen Flächen des Kanalbereichs ausgebildet ist und das über dem unteren Isolator und nicht über den ersten und zweiten Abschnitten der unteren SiGe-Schicht angeordnet ist, wobei das Ersatz-Gate durch das konforme Dielektrikum von den extrinsischen S/D-Bereichen elektrisch getrennt ist.

公开(公告)号：DE602004026063D1

公开(公告)日：2010-04-29

申请号：DE602004026063

申请日：2004-06-25

Applicant: IBM

Inventor： NOWAK EDWARD J

IPC: H01L27/108 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/119

Abstract: The invention provides a method of manufacturing a fin-type field effect transistor (FinFET) that forms a unique FinFET that has a first fin with a central channel region and source and drain regions adjacent the channel region, a gate intersecting the first fin and covering the channel region, and a second fin having only a channel region.

公开(公告)号：DE602004015592D1

公开(公告)日：2008-09-18

申请号：DE602004015592

申请日：2004-01-30

Applicant: IBM

Inventor： RAINEY BETH ANN ,  NOWAK EDWARD J ,  ALLER INGO DR ,  KEINERT JOACHIM ,  LUDWIG THOMAS

IPC: H01L21/336 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04 ,  H01L29/786

Abstract: The present invention provides a FinFET device that has a first fin and a second fin. Each fin has a channel region and source and drain regions that extend from the channel region. The fins have different heights. The invention has a gate conductor positioned adjacent the fins. The gate conductor runs perpendicular to the fins and crosses the channel region of each of the first fin and second fin. The fins are parallel to one another. The ratio of the height of the first fin to the height of the second fin comprises a ratio of one to 2/3. The ratio is used to tune the performance of the transistor and determines the total channel width of the transistor.

公开(公告)号：AU2003297751A1

公开(公告)日：2005-07-21

申请号：AU2003297751

申请日：2003-12-08

Applicant: IBM

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  ANDERSON BRENT A

IPC: H01L21/336 ,  H01L27/11 ,  H01L27/12 ,  H01L27/148 ,  H01L29/786

Abstract: An integrated circuit semiconductor memory device having the BOX layer removed from under the gate of a storage transistor to increase the gate-to-substrate capacitance and reduce the soft error rate. The increased node capacitance thus obtained is achieved without requiring a corresponding increase in area.

公开(公告)号：AU2003293380A1

公开(公告)日：2004-07-29

申请号：AU2003293380

申请日：2003-12-05

Applicant: IBM

Inventor： NOWAK EDWARD J ,  RAINEY BETHANN

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

Abstract: A MOS device with first and second freestanding semiconductor bodies formed on a substrate. The first freestanding semiconductor body has a first portion thereof disposed at a non-orthogonal, non parallel orientation with respect to a first portion of the second freestanding semiconductor body. These portions of said first and second freestanding semiconductor bodies have respective first and second crystalline orientations. A first gate electrode crosses over at least part of said first portion of said first freestanding semiconductor body at a non-orthogonal angle, as does a second gate electrode over the first portion of the second freestanding semiconductor body.

公开(公告)号：CA2757818C

公开(公告)日：2019-12-10

申请号：CA2757818

申请日：2010-06-02

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/78

Abstract: A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates (16 of FIG. 6) about a plurality of active regions and depositing a dielectric material (18a and in space 20) over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material (20) to expose the temporary spacer gates (16) and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material (18a). The method additionally includes filling the space (20) between the active regions and above the remaining portion of the dielectric material (18a) with a gate material.

公开(公告)号：GB2503806B

公开(公告)日：2016-03-09

申请号：GB201311356

申请日：2013-01-28

Applicant: IBM

Inventor： NOWAK EDWARD J ,  ANDERSON BRENT ALAN ,  BRYANT ANDRES

IPC: H01L29/66 ,  H01L29/78

Abstract: A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region.

公开(公告)号：GB2487321B

公开(公告)日：2013-12-11

申请号：GB201205682

申请日：2010-10-19

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/28

Abstract: The present invention relates generally to semiconductor devices and, more specifically, to damascene gates having protected shorting regions and related methods for their manufacture. A first aspect of the invention provides a method of forming a damascene gate with protected shorting regions, the method comprising: forming a damascene gate having: a gate dielectric atop a substrate; a gate conductor atop the gate dielectric; a conductive liner laterally adjacent the gate conductor; a spacer between the conductive liner and the substrate; and a first dielectric atop the gate conductor; removing a portion of the conductive liner; and depositing a second dielectric atop a remaining portion of the conductive liner, such that the second dielectric is laterally adjacent both the first dielectric and the gate.

公开(公告)号：CA2757818A1

公开(公告)日：2010-12-29

申请号：CA2757818

申请日：2010-06-02

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J

IPC: H01L21/336 ,  H01L29/78

Abstract: A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates (16 of FIG. 6) about a plurality of active regions and depositing a dielectric material (18a and in space 20) over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material (20) to expose the temporary spacer gates (16) and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material (18a). The method additionally includes filling the space (20) between the active regions and above the remaining portion of the dielectric material (18a) with a gate material.