公开(公告)号：US20220199402A1

公开(公告)日：2022-06-23

申请号：US17133079

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Koustav Ganguly ,  Ryan Keech ,  Harold Kennel ,  Willy Rachmady ,  Ashish Agrawal ,  Glenn Glass ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L21/02 ,  H01L29/16 ,  H01L27/092 ,  H01L29/78

Abstract: High-purity Ge channeled N-type transistors include a Si-based barrier material separating the channel from a Ge source and drain that is heavily doped with an N-type impurity. The barrier material may have nanometer thickness and may also be doped with N-type impurities. Because of the Si content, N-type impurities have lower diffusivity within the barrier material and can be prevented from entering high-purity Ge channel material. In addition to Si, a barrier material may also include C. With the barrier material, an N-type transistor may display higher channel mobility and reduced short-channel effects.

公开(公告)号：US11335793B2

公开(公告)日：2022-05-17

申请号：US16957667

申请日：2018-02-28

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Jack Kavalieros ,  Ian Young ,  Matthew Metz ,  Willy Rachmady ,  Uygar Avci ,  Ashish Agrawal ,  Benjamin Chu-Kung

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786

Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.

公开(公告)号：US20220093586A1

公开(公告)日：2022-03-24

申请号：US17540120

申请日：2021-12-01

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US11276644B2

公开(公告)日：2022-03-15

申请号：US16221798

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish Agrawal ,  Kevin Lin ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan

IPC: H01L23/532 ,  H01L29/45 ,  H01L29/786 ,  H01L23/522 ,  H01L21/768 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L21/285

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

公开(公告)号：US20210036023A1

公开(公告)日：2021-02-04

申请号：US16529643

申请日：2019-08-01

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Jack Kavalieros ,  Anand Murthy ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Cheng-Ying Huang ,  Cory Bomberger

IPC: H01L27/12 ,  H01L29/08 ,  H01L29/417 ,  H01L29/10 ,  H01L29/66

Abstract: Thin film transistor structures may include a regrown source or drain material between a channel material and source or drain contact metallization. The source or drain material may be selectively deposited at low temperatures to backfill recesses formed in the channel material. Electrically active dopant impurities may be introduced in-situ during deposition of the source or drain material. The source or drain material may overlap a portion of a gate electrode undercut by the recesses. With channel material of a first composition and source or drain material of a second composition, thin film transistor structures may display low external resistance and high channel mobility.

公开(公告)号：US20190305085A1

公开(公告)日：2019-10-03

申请号：US15942252

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Seung Hoon Sung ,  Dipanjan Basu ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Siddharth Chouksey ,  Cory C. Bomberger ,  Tahir Ghani ,  Anand S. Murthy ,  Jack T. Kavalieros

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16

Abstract: An integrated circuit structure includes: a semiconductor nanowire extending in a length direction and including a body portion; a gate dielectric surrounding the body portion; a gate electrode insulated from the body portion by the gate dielectric; a semiconductor source portion adjacent to a first side of the body portion; and a semiconductor drain portion adjacent to a second side of the body portion opposite the first side, the narrowest dimension of the second side of the body portion being smaller than the narrowest dimension of the first side. In an embodiment, the nanowire has a conical tapering. In an embodiment, the gate electrode extends along the body portion in the length direction to the source portion, but not to the drain portion. In an embodiment, the drain portion at the second side of the body portion has a lower dopant concentration than the source portion at the first side.

公开(公告)号：US20190273133A1

公开(公告)日：2019-09-05

申请号：US16347110

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Siddharth Chouksey ,  Glenn A. Glass ,  Van H. Le ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Willy Rachmady

IPC: H01L29/08 ,  H01L29/165 ,  H01L29/16 ,  H01L29/36 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L29/45 ,  H01L29/417 ,  H01L29/10

Abstract: Disclosed herein are transistor amorphous interlayer arrangements, and related methods and devices. For example, in some embodiments, transistor amorphous interlayer arrangement may include a channel material and a transistor source/drain stack. The transistor source/drain stack may include a transistor electrode material configured to be a transistor source/drain contact, i.e. either a source contact or a drain contact of the transistor, and a doped amorphous semiconductor material disposed between the transistor electrode material and the channel material.

公开(公告)号：US10347767B2

公开(公告)日：2019-07-09

申请号：US15570742

申请日：2015-06-16

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Ashish Agrawal

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06

Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.