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    Semiconductor memory with embedded dram
    73.
    发明公开
    Semiconductor memory with embedded dram 有权
    Halbleiterspeicher mit eingebettetem DRAM-Speicher

    公开(公告)号：EP1422719A2

    公开(公告)日：2004-05-26

    申请号：EP03103920.9

    申请日：2003-10-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  MICHELONI, Rino

    IPC: G11C11/00

    CPC classification number: G11C11/005

    Abstract: A semiconductor memory comprises a plurality of memory cells (MC), for example Flash memory cells, arranged in a plurality of lines (LBL), and a plurality of memory cell access signal lines (MBL), each one associated with at least one respective line of memory cells, for accessing the memory cells of the at least one respective line of memory cells; each signal line has a capacitance (CMBL) intrinsically associated therewith. A plurality of volatile memory cells is provided, each having a capacitive storage element. Each volatile memory cell is associated with a respective signal line, and the respective capacitive storage element formed by the capacitance intrinsically associated with the respective signal lines. In particular, the parasitic capacitances associated with bit lines of a matrix of memory cells can be exploited as capacitive storage elements.

    Abstract translation: 半导体存储器包括布置在多行（LBL）中的多个存储单元（MC），例如闪存单元，以及多个存储单元存取信号线（MBL），每个存储单元与至少一个相应的存储单元 存储单元行，用于访问所述至少一个相应行的存储器单元的存储单元; 每个信号线具有与其本征相关联的电容（CMBL）。 提供了多个易失性存储单元，每个易失性存储单元均具有电容存储元件。 每个易失性存储器单元与相应的信号线相关联，并且由与各个信号线固有相关联的电容形成的相应电容存储元件。 特别地，与存储器单元的矩阵的位线相关联的寄生电容可以被用作电容性存储元件。

    Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell
    80.
    发明公开
    Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell 有权
    一种方法和电路，用于存储单元的动态阅读，尤其是非易失性的多位

    公开(公告)号：EP1225595A1

    公开(公告)日：2002-07-24

    申请号：EP01830017.8

    申请日：2001-01-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C11/56 ,  G11C16/26 ,  G11C7/06

    CPC classification number: G11C11/5621 ,  G11C7/067 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26

    Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell (36) by a capacitive element (22, 23). The capacitive element (22, 23) is initially charged and then discharged linearly in a preset time, while the memory cell (36) is biased at a constant voltage. In a first operating mode, initially a first capacitor (22) and a second capacitor (23) are respectively charged to a first charge value and to a second charge value. The second capacitor (23) is discharged through the memory cell (36) at a constant current in a preset time; the first charge is shared between the first capacitor (22) and the second capacitor (23); and then the shared charge is measured.

    Abstract translation: 用于读取存储器单元的方法，在由电容元件（22，23）提供到所述存储器单元（36）的电流的时间是基于集成。 电容元件（22，23）进行初始充电，然后在预置的时间线性地排出，同时所述存储器单元（36）以恒定的电压被偏置。 在第一种操作模式中，最初为第一电容器（22）和第二电容器（23）被充电到第一充电值和第二电荷值分别。 所述第二电容器（23）通过在预先设定的时间的恒定电流的存储单元（36）中排出; 第一电荷在第一电容器（22）和第二电容器（23）之间共享的; 然后共享电荷进行测量。

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