Abstract:
The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell (36) by a capacitive element (22, 23). The capacitive element (22, 23) is initially charged and then discharged linearly in a preset time, while the memory cell (36) is biased at a constant voltage. In a first operating mode, initially a first capacitor (22) and a second capacitor (23) are respectively charged to a first charge value and to a second charge value. The second capacitor (23) is discharged through the memory cell (36) at a constant current in a preset time; the first charge is shared between the first capacitor (22) and the second capacitor (23); and then the shared charge is measured.
Abstract:
The read circuit (1') comprises an array branch (6) having an input array node (22) connected, via an array bit line (8), to an array cell (10); a reference branch (12) having an input reference node (32) connected, via a reference bit line (14), to a reference cell (16); a current-to-voltage converter (18) connected to an output array node (56) of the array branch (6) and to an output reference node (58) of the reference branch (12) to supply on the output array node (56) and the output reference node (58) the respective electric potentials (V M , V R ) correlated to the currents flowing in the array memory cell (10) and, respectively, in the reference memory cell (16); and a comparator (19) connected at input to the output array node (56) and output reference node (58) and supplying as output a signal (OUT) indicative of the contents stored in the array memory cell (10); and an array decoupling stage (80) arranged between the input array node (22) and the output array node (56) to decouple the electric potentials of the input and output array nodes (22, 56) from one another.
Abstract:
The row decoder includes, for each word line (WL) of the memory (2), a respective biasing circuit (54) receiving at the input a row selection signal (SR ) switching, in preset operating conditions, between a supply voltage (V CC ) and a ground voltage (V GND ) and supplying at the output a biasing signal (R ) for the respective word line (WL) switching between a first operating voltage (V PC ), in turn switching at least between the supply voltage (V CC ) and a programming voltage (V PP ) higher than the supply voltage (V CC ), and a second operating voltage (V NEG ), in turn switching at least between the ground voltage (V GND ) and an erase voltage (V ERN ) lower than the ground voltage (V GND ). Each biasing circuit (54) includes a level translator circuit (58) receiving at the input the row selection signal (SR ) and supplying as output a control signal (CM ) switching between the first and the second operating voltages (V PC , V NEG ) and an output driver circuit (60) receiving as input the control signal (CM ) and supplying at the output the biasing signal (R ).
Abstract:
The switch circuit (40) receives a first supply voltage (V CC ) and a second supply voltage (V PP ) different from each other; a control input (41a) receiving a control signal that may be switched between the first supply voltage and ground; a driving inverter stage (44) supplied by the second supply voltage (V PP ) and defining the output (70) of the circuit; a feedback inverter stage (43) supplied by the second supply voltage and including a top transistor (51) and a bottom transistor (53) defining an intermediate node (58) and having respective control terminals. The control terminal of the top transistor (51) is connected to the output node (70), the control terminal of the bottom transistor (53) is connected to the control input (41a), and the intermediate node is connected to the input (58) of the driving inverter stage. An activation element (80, 71) helps switching of the intermediate node (58) from the second supply voltage to ground; current limiting transistors (52, 62) are arranged in the inverter stages to limit the current flowing during switching and to reduce the consumption of the circuit.
Abstract:
The invention relates to a circuit device for carrying out a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and comprising at least one matrix of memory cells (5) with sectors (3,4) organized into columns, wherein each sector has a specific group of local word lines (LWL) individually connected to a main word line (MWL) running through all of the matrix sectors which have rows in common. The device comprises a first transistor (M1) of the PMOS type having its conduction terminals connected, the one to the main word line (MWL) and the other to the local word line (LWL), and a second transistor (M3) of the NMOS type having its conduction terminals connected, the one to the local word line (LWL) and the other to a reference voltage (GND).
Abstract:
The invention relates to a row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, being of the type adapted to boost, through at least one boost capacitor (Cboost), a read voltage to be applied to a memory column containing a memory cell to be read. The circuit is powered between a first supply voltage reference (Vpcx) and a second ground potential reference (GND), and comprises a hierarchic structure (13) of cascade connected inverters (15,16) and a circuit means of progressively raising the read voltage level dynamically. First means (Cboost0,D1) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus a threshold voltage (Vtp), and second means (Cboost1,D2) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus twice said threshold voltage (Vtp).
Abstract:
The row decoder comprises a plurality of pre-decoding circuits (14, 15) which, starting from row addresses, generate pre-decoding signals and a plurality of final decoding circuits (12) which, starting from the pre-decoding signals, drive the individual rows of the array (2). Each pre-decoding circuit (10) has a push-pull output circuit with a pull-up transistor (42) and a pull-down transistor (44) and four parallel paths for the signal, a first path (50), supplied with low voltage, which drives the pull-up transistor during reading; a second path (52), supplied with a positive high voltage, which drives the pull-up transistor during programming and erasing; a third path (100), supplied with a low voltage, which drives the pull-down transistor during reading and programming; and a fourth path (102), supplied with a negative high voltage, which drives the pull-down transistor during erasing. Two selection stages (54, 104) enable selectively one of the first and second path (50, 52), and one of the third and fourth path (100, 102), depending on the operative step.