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    Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell
    71.
    发明公开
    Method and circuit for dynamic reading of a memory cell, in particular a multi-level nonvolatile memory cell 有权
    一种方法和电路，用于存储单元的动态阅读，尤其是非易失性的多位

    公开(公告)号：EP1225595A1

    公开(公告)日：2002-07-24

    申请号：EP01830017.8

    申请日：2001-01-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C11/56 ,  G11C16/26 ,  G11C7/06

    CPC classification number: G11C11/5621 ,  G11C7/067 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26

    Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell (36) by a capacitive element (22, 23). The capacitive element (22, 23) is initially charged and then discharged linearly in a preset time, while the memory cell (36) is biased at a constant voltage. In a first operating mode, initially a first capacitor (22) and a second capacitor (23) are respectively charged to a first charge value and to a second charge value. The second capacitor (23) is discharged through the memory cell (36) at a constant current in a preset time; the first charge is shared between the first capacitor (22) and the second capacitor (23); and then the shared charge is measured.

    Abstract translation: 用于读取存储器单元的方法，在由电容元件（22，23）提供到所述存储器单元（36）的电流的时间是基于集成。 电容元件（22，23）进行初始充电，然后在预置的时间线性地排出，同时所述存储器单元（36）以恒定的电压被偏置。 在第一种操作模式中，最初为第一电容器（22）和第二电容器（23）被充电到第一充电值和第二电荷值分别。 所述第二电容器（23）通过在预先设定的时间的恒定电流的存储单元（36）中排出; 第一电荷在第一电容器（22）和第二电容器（23）之间共享的; 然后共享电荷进行测量。

    Read circuit for a nonvolatile memory
    73.
    发明公开
    Read circuit for a nonvolatile memory 有权
    发言人LeseschaltungfüreinennichtflüchtigenSpeicher

    公开(公告)号：EP1071096A1

    公开(公告)日：2001-01-24

    申请号：EP99830469.5

    申请日：1999-07-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Crippa, Luca

    IPC: G11C16/28 ,  G11C7/06

    CPC classification number: G11C16/28

    Abstract: The read circuit (1') comprises an array branch (6) having an input array node (22) connected, via an array bit line (8), to an array cell (10); a reference branch (12) having an input reference node (32) connected, via a reference bit line (14), to a reference cell (16); a current-to-voltage converter (18) connected to an output array node (56) of the array branch (6) and to an output reference node (58) of the reference branch (12) to supply on the output array node (56) and the output reference node (58) the respective electric potentials (V M , V R ) correlated to the currents flowing in the array memory cell (10) and, respectively, in the reference memory cell (16); and a comparator (19) connected at input to the output array node (56) and output reference node (58) and supplying as output a signal (OUT) indicative of the contents stored in the array memory cell (10); and an array decoupling stage (80) arranged between the input array node (22) and the output array node (56) to decouple the electric potentials of the input and output array nodes (22, 56) from one another.

    Abstract translation: 读取电路（1'）包括具有通过阵列位线（8）连接到阵列单元（10）的输入阵列节点（22）的阵列分支（6）。 具有通过参考位线（14）连接到参考单元（16）的输入参考节点（32）的参考分支（12）; 连接到阵列分支（6）的输出阵列节点（56）和参考分支（12）的输出参考节点（58）的电流 - 电压转换器（18），以在输出阵列节点 56）和输出参考节点（58）分别与在阵列存储单元（10）中流动的电流和参考存储单元（16）相关的电位相关联的各个电位（VM，VR）; 以及比较器（19），其在输入端连接到输出阵列节点（56）和输出参考节点（58），并且作为输出提供指示存储在阵列存储单元（10）中的内容的信号（OUT）。 以及布置在所述输入阵列节点（22）和所述输出阵列节点（56）之间的阵列解耦级（80），以将所述输入和输出阵列节点（22,56）的电位彼此去耦。

    Row decoder for a nonvolatile memory with possibility of selectively biasing word lines to positive or negative voltages
    74.
    发明公开
    Row decoder for a nonvolatile memory with possibility of selectively biasing word lines to positive or negative voltages 有权
    行解码器，用于非易失性存储器为字线随机正和负偏置调整

    公开(公告)号：EP1061525A1

    公开(公告)日：2000-12-20

    申请号：EP99830378.8

    申请日：1999-06-17

    Applicant: STMicroelectronics S.r.l. ,  Mitsubishi Electric Corporation

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ohba, Atsushi, c/o Mitsubishi Denki K. K. ,  Carrera, Marcello

    IPC: G11C16/12 ,  G11C8/00

    CPC classification number: G11C11/5621 ,  G11C8/08 ,  G11C8/14 ,  G11C16/08 ,  G11C16/12 ,  G11C16/30

    Abstract: The row decoder includes, for each word line (WL) of the memory (2), a respective biasing circuit (54) receiving at the input a row selection signal (SR ) switching, in preset operating conditions, between a supply voltage (V CC ) and a ground voltage (V GND ) and supplying at the output a biasing signal (R ) for the respective word line (WL) switching between a first operating voltage (V PC ), in turn switching at least between the supply voltage (V CC ) and a programming voltage (V PP ) higher than the supply voltage (V CC ), and a second operating voltage (V NEG ), in turn switching at least between the ground voltage (V GND ) and an erase voltage (V ERN ) lower than the ground voltage (V GND ). Each biasing circuit (54) includes a level translator circuit (58) receiving at the input the row selection signal (SR ) and supplying as output a control signal (CM ) switching between the first and the second operating voltages (V PC , V NEG ) and an output driver circuit (60) receiving as input the control signal (CM ) and supplying at the output the biasing signal (R ).

    Abstract translation: 行译码器包括，用于存储器（2），一个respectivement偏置电路（54）的每个字线（WL）在所述输入端接收一个行选择信号（SR的）的切换，在预先设定的操作条件下，一个电源之间 电压（VCC）和地电压（V GND），并在输出端供给的respectivement字线的第一工作电压（VPC）之间进行切换的偏置信号（R ）（WL），依次之间至少切换 电源电压（VCC）和一个编程电压（VPP）高于电源电压（VCC），和第二操作电压（VNEG），继而至少接地电压（V GND）和擦除电压（VERN）低之间切换更高 比接地电压（V GND）。 每个偏置电路（54）包括：在输入端接收所述行选择信号（SR的）和供应作为输出的控制信号的电平转换电路（58）（CM的）在第一和第二工作电压之间的切换 （VPC，VNEG）和接收作为输入的控制信号输出驱动器电路（60）（CM的），并在输出端供给所述偏压信号（R ）。

    CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching
    75.
    发明公开
    CMOS switch circuit for transferring high voltages, in particular for line decoding in nonvolatile memories, with reduced consumption during switching 有权
    CMOS开关期间在非易失性存储器的低功耗切换用于传输高电压，特别是对行译码器

    公开(公告)号：EP1058271A1

    公开(公告)日：2000-12-06

    申请号：EP99830345.7

    申请日：1999-06-04

    Applicant: STMicroelectronics S.r.l. ,  Mitsubishi Electric Corporation

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ohba, Atsushi, c/o Mitsubishi Denki K. K. ,  Carrera, Marcello

    IPC: G11C16/12 ,  H03K19/017

    CPC classification number: H03K19/018521 ,  G11C5/145 ,  G11C8/10 ,  G11C11/5621 ,  G11C16/08 ,  H03K19/0013 ,  H03K19/01721

    Abstract: The switch circuit (40) receives a first supply voltage (V CC ) and a second supply voltage (V PP ) different from each other; a control input (41a) receiving a control signal that may be switched between the first supply voltage and ground; a driving inverter stage (44) supplied by the second supply voltage (V PP ) and defining the output (70) of the circuit; a feedback inverter stage (43) supplied by the second supply voltage and including a top transistor (51) and a bottom transistor (53) defining an intermediate node (58) and having respective control terminals. The control terminal of the top transistor (51) is connected to the output node (70), the control terminal of the bottom transistor (53) is connected to the control input (41a), and the intermediate node is connected to the input (58) of the driving inverter stage. An activation element (80, 71) helps switching of the intermediate node (58) from the second supply voltage to ground; current limiting transistors (52, 62) are arranged in the inverter stages to limit the current flowing during switching and to reduce the consumption of the circuit.

    Abstract translation: 开关电路（40）接收第一供给电压（VCC）和第二电源电压（VPP）从海誓山盟不同; 接收控制信号的控制输入端（41）可以被切换所述第一电源电压和地之间做; 由第二电源电压（VPP）和，定义电路的输出（70）提供的驱动逆变器级（44）; 由第二电源电压供电，并且包括一个顶部晶体管（51）和上限定中间节点（58）和具有respectivement控制端子的底部晶体管（53）的反馈逆变器级（43）。 顶部晶体管的控制端子（51）被连接到被连接到控制输入端（41A）和中间节点的输出节点（70），底部晶体管的控制端子（53）被连接到输入端（ 驱动用逆变器级的58）。 致动元件（80，71）可帮助从所述第二电源电压到地的中间节点（58）的切换; 限流晶体管（52，62）被布置在所述逆变器级，以限制流过的电流在开关期间，并减少了电路的功耗。

    Circuit device for providing a hierarchical row decoding in semiconductor memory devices
    76.
    发明公开
    Circuit device for providing a hierarchical row decoding in semiconductor memory devices 有权
    萨尔瓦多桑诺·祖尔等级Zellendekodierung einer Halbleiterspeicheranordnung

    公开(公告)号：EP0991075A1

    公开(公告)日：2000-04-05

    申请号：EP98830570.2

    申请日：1998-09-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C8/00

    CPC classification number: G11C16/0416 ,  G11C8/14

    Abstract: The invention relates to a circuit device for carrying out a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and comprising at least one matrix of memory cells (5) with sectors (3,4) organized into columns, wherein each sector has a specific group of local word lines (LWL) individually connected to a main word line (MWL) running through all of the matrix sectors which have rows in common. The device comprises a first transistor (M1) of the PMOS type having its conduction terminals connected, the one to the main word line (MWL) and the other to the local word line (LWL), and a second transistor (M3) of the NMOS type having its conduction terminals connected, the one to the local word line (LWL) and the other to a reference voltage (GND).

    Abstract translation: 本发明涉及一种用于在非易失性类型的半导体存储器件中执行行解码的分层形式的电路装置，并且包括至少一个具有组织成列的扇区（3,4）的存储器单元（5）的矩阵，其中 每个扇区具有单独连接到贯穿所有具有公共行的矩阵扇区的主字线（MWL）的特定组的本地字线（LWL）。 该器件包括PMOS型的第一晶体管（M1），其导通端子连接到主字线（MWL），另一端连接到本地字线（LWL），第二晶体管（M3） 其导体端子连接的NMOS类型，一个连接到本地字线（LWL），另一个连接到参考电压（GND）。

    Row decoder circuit for an electronic memory device, particularly for low voltage applications
    77.
    发明公开
    Row decoder circuit for an electronic memory device, particularly for low voltage applications 失效
    行解码器，用于电子存储器装置，特别是用于低压供电

    公开(公告)号：EP0928003A3

    公开(公告)日：2000-01-12

    申请号：EP98114061.9

    申请日：1998-07-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ferrario, Donato ,  Ghezzi, Stefano

    IPC: G11C8/00 ,  G11C11/408

    CPC classification number: G11C8/08 ,  G11C11/4085

    Abstract: The invention relates to a row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, being of the type adapted to boost, through at least one boost capacitor (Cboost), a read voltage to be applied to a memory column containing a memory cell to be read. The circuit is powered between a first supply voltage reference (Vpcx) and a second ground potential reference (GND), and comprises a hierarchic structure (13) of cascade connected inverters (15,16) and a circuit means of progressively raising the read voltage level dynamically. First means (Cboost0,D1) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus a threshold voltage (Vtp), and second means (Cboost1,D2) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus twice said threshold voltage (Vtp).

    Row decoder for a flash-EEPROM memory device with the possibility of selective erasing of a sub-group of rows of a sector
    78.
    发明公开
    Row decoder for a flash-EEPROM memory device with the possibility of selective erasing of a sub-group of rows of a sector 失效
    行译码器对于快闪EEPROM存储器阵列的扇区的行子集的选择性缺失的可能性

    公开(公告)号：EP0920023A1

    公开(公告)日：1999-06-02

    申请号：EP97830625.6

    申请日：1997-11-26

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Micheloni, Rino

    IPC: G11C8/00 ,  G11C16/06

    CPC classification number: G11C16/08

    Abstract: The row decoder comprises a plurality of pre-decoding circuits (14, 15) which, starting from row addresses, generate pre-decoding signals and a plurality of final decoding circuits (12) which, starting from the pre-decoding signals, drive the individual rows of the array (2). Each pre-decoding circuit (10) has a push-pull output circuit with a pull-up transistor (42) and a pull-down transistor (44) and four parallel paths for the signal, a first path (50), supplied with low voltage, which drives the pull-up transistor during reading; a second path (52), supplied with a positive high voltage, which drives the pull-up transistor during programming and erasing; a third path (100), supplied with a low voltage, which drives the pull-down transistor during reading and programming; and a fourth path (102), supplied with a negative high voltage, which drives the pull-down transistor during erasing. Two selection stages (54, 104) enable selectively one of the first and second path (50, 52), and one of the third and fourth path (100, 102), depending on the operative step.

    Abstract translation: 行解码器包括预解码电路（14，15）的复数，从行地址开始，生成预解码信号和最终解码电路的多个（12）其中，从预译码信号开始，驱动 该阵列的各行（2）。 每个预解码电路（10）具有与提供一个上拉晶体管（42）和一个下拉晶体管（44）和用于将信号四个平行路径，第一路径（50）的推挽输出电路 低电压，其读取期​​间驱动所述上拉晶体管; 具有正的高电压，其驱动编程和擦除期间，上拉晶体管提供第二路径（52）; 具有低电压，其读出和编程期间驱动所述下拉晶体管提供的第三路径（100）; 和第四路径（102），提供有负的高电压，其擦除期间驱动下拉晶体管。 两个选择阶段（54，104）使能选择性地将第一和第二路径中的一个（50，52）和所述第三和第四路径中的一个（100,102），根据操作步骤。

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