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    Protection for an integrated circuit
    73.
    发明授权
    Protection for an integrated circuit 有权
    保护集成电路

    公开(公告)号：US08390971B2

    公开(公告)日：2013-03-05

    申请号：US13063189

    申请日：2009-09-09

    Applicant: Hans-Martin Ritter ,  Ingo Laasch

    Inventor： Hans-Martin Ritter ,  Ingo Laasch

    IPC: H02H3/20 ,  H02H3/22 ,  H02H9/00

    CPC classification number: H01L27/0248 ,  H01L23/60 ,  H01L2924/0002 ,  H05K1/0259 ,  H05K2201/0784 ,  H01L2924/00

    Abstract: The present invention relates to a discharge structure for an overvoltage and/or overcurrent protection, in particular to a discharge structure for an electrostatic discharge (ESD) protection, for an integrated circuit (IC), and to an ESD protection device for an IC comprising such a discharge structure and to a method for making such a structure. The present invention particularly relates to such a discharge structure (50, 52) which comprises at least two discharge paths (40, 80) provided to conduct a current to a terminal (60), whereas substantially all of the discharge paths (40, 80) present substantially the same resistance for the current.

    Abstract translation: 本发明涉及一种用于过电压和/或过电流保护的放电结构，特别涉及一种用于集成电路（IC）的静电放电（ESD）保护用放电结构以及用于IC的ESD保护器件的放电结构，包括 这种放电结构和制造这种结构的方法。 本发明特别涉及一种这样的放电结构（50,52），其包括设置成将电流传导到端子（60）的至少两个放电路径（40,80），而基本上所有的放电路径（40,80） ）对于电流呈现大致相同的电阻。

    TRACE BORDER ROUTING
    74.
    发明申请
    TRACE BORDER ROUTING 有权
    跟踪边界路由

    公开(公告)号：US20120092273A1

    公开(公告)日：2012-04-19

    申请号：US13007493

    申请日：2011-01-14

    Applicant: Benjamin B. LYON ,  Shih Chang CHANG ,  Martin Paul GRUNTHANER

    Inventor： Benjamin B. LYON ,  Shih Chang CHANG ,  Martin Paul GRUNTHANER

    IPC: G06F3/041 ,  H05K3/10

    CPC classification number: H05K1/0242 ,  G06F3/0412 ,  G06F3/0416 ,  G06F2203/04108 ,  G09G3/2092 ,  H05K1/0265 ,  H05K2201/0784 ,  H05K2201/09272 ,  H05K2201/09727 ,  Y10T29/49155

    Abstract: The border routing of conductive traces in devices, such as displays, touch sensor panels, and touch screens, to improve border area space usage, thereby reducing device size, and to reduce trace resistance, thereby improving device operation, is disclosed. The conductive traces can form a staggered stair-step configuration in the device border area, in which the average widths of the traces can be different from each other and each trace can have segments with different widths. The conductive traces can be coupled to an active area of the device to transmit signals to and from the active area in accordance with a device operation. The varying widths can help improve the border area space usage, reduce trace resistance, and reduce the differences in resistance between traces.

    Abstract translation: 公开了诸如显示器，触摸传感器面板和触摸屏等设备中导电迹线的边界布线，以改善边界区域空间的使用，从而减少设备尺寸，并降低走线电阻，从而改善器件的操作。 导电迹线可以在器件边界区域中形成交错的阶梯结构，其中迹线的平均宽度可以彼此不同，并且每个迹线可以具有不同宽度的段。 导电迹线可以耦合到设备的有效区域，以根据设备操作向有源区域发送信号和从有源区域发送信号。 变化的宽度可以帮助改善边界区域空间的使用，减少走线电阻，并减少迹线之间的电阻差异。

    PROTECTION FOR AN INTEGRATED CIRCUIT
    75.
    发明申请
    PROTECTION FOR AN INTEGRATED CIRCUIT 有权
    集成电路的保护

    公开(公告)号：US20110216459A1

    公开(公告)日：2011-09-08

    申请号：US13063189

    申请日：2009-09-09

    Applicant: Hans-Martin Ritter ,  Ingo Laasch

    Inventor： Hans-Martin Ritter ,  Ingo Laasch

    IPC: H02H3/20

    CPC classification number: H01L27/0248 ,  H01L23/60 ,  H01L2924/0002 ,  H05K1/0259 ,  H05K2201/0784 ,  H01L2924/00

    Abstract: The present invention relates to a discharge structure for an overvoltage and/or overcurrent protection, in particular to a discharge structure for an electrostatic discharge (ESD) protection, for an integrated circuit (IC), and to an ESD protection device for an IC comprising such a discharge structure and to a method for making such a structure. The present invention particularly relates to such a discharge structure (50, 52) which comprises at least two discharge paths (40, 80) provided to conduct a current to a terminal (60), whereas substantially all of the discharge paths (40, 80) present substantially the same resistance for the current.

    Abstract translation: 本发明涉及一种用于过电压和/或过电流保护的放电结构，特别涉及一种用于集成电路（IC）的静电放电（ESD）保护用放电结构以及用于IC的ESD保护器件的放电结构，包括 这种放电结构和制造这种结构的方法。 本发明特别涉及一种这样的放电结构（50,52），其包括设置成将电流传导到端子（60）的至少两个放电路径（40,80），而基本上所有的放电路径（40,80） ）对于电流呈现大致相同的电阻。

    INTERCONNECTION LINE DEVICE, IMAGE DISPLAY APPARATUS, AND METHOD FOR MANUFACTURING INTERCONNECTION LINE DEVICE
    76.
    发明申请
    INTERCONNECTION LINE DEVICE, IMAGE DISPLAY APPARATUS, AND METHOD FOR MANUFACTURING INTERCONNECTION LINE DEVICE 有权
    互连线装置，图像显示装置和制造互连线装置的方法

    公开(公告)号：US20100066709A1

    公开(公告)日：2010-03-18

    申请号：US12561343

    申请日：2009-09-17

    Applicant: AKIHIRO YAJIMA

    Inventor： AKIHIRO YAJIMA

    IPC: G09G5/00 ,  H05K1/11 ,  H05K1/16 ,  H05K3/42

    CPC classification number: H05K1/117 ,  G02F1/1345 ,  H05K1/0263 ,  H05K2201/0784 ,  H05K2201/09263 ,  H05K2201/09481 ,  H05K2201/09727 ,  Y10T29/49147

    Abstract: An interconnection line device includes an insulating layer for electrical insulation; an external connection terminal which is formed on one surface of the insulating layer: an interconnection line which is formed on another surface of the insulating layer and whose one end portion area is connected to a predetermined signal line; and a connection portion which is arranged so as to penetrate through the insulating layer and connects another end portion area of the interconnection line to the external connection terminal.

    Abstract translation: 互连线器件包括用于电绝缘的绝缘层; 形成在所述绝缘层的一个表面上的外部连接端子：形成在所述绝缘层的另一个表面上并且其一个端部区域连接到预定信号线的互连线; 以及连接部，其被布置成穿过绝缘层并且将互连线的另一端部区域连接到外部连接端子。

    DISPLAY DEVICE
    79.
    发明申请
    DISPLAY DEVICE 审中-公开
    显示设备

    公开(公告)号：US20160374193A1

    公开(公告)日：2016-12-22

    申请号：US14992846

    申请日：2016-01-11

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jun Namkung

    IPC: H05K1/02 ,  H05K1/11 ,  H05K5/00

    CPC classification number: H05K1/0213 ,  G02F1/13452 ,  H05K1/147 ,  H05K2201/0784 ,  H05K2201/09263 ,  H05K2201/10128

    Abstract: A display device is disclosed. In one aspect, the display device includes a first substrate including a display area configured to display an image and a first pad region neighboring the display area. The display device also includes a second substrate including a second pad region. The second pad region includes a driving circuit. The display device also includes a connector connecting the first pad region to the second pad region, the connector including a wiring that electrically connects the display area to the driving circuit.

    Abstract translation: 公开了一种显示装置。 一方面，显示装置包括：第一基板，包括被配置为显示图像的显示区域和与显示区域相邻的第一焊盘区域。 显示装置还包括包括第二垫区域的第二基板。 第二焊盘区域包括驱动电路。 显示装置还包括将第一焊盘区域连接到第二焊盘区域的连接器，连接器包括将显示区域电连接到驱动电路的布线。

    REDUCING TRACE LENGTH AND INSERTION LOSS OF HIGH SPEED SIGNALS ON A NETWORK SWITCH BOARD
    80.
    发明申请
    REDUCING TRACE LENGTH AND INSERTION LOSS OF HIGH SPEED SIGNALS ON A NETWORK SWITCH BOARD 审中-公开
    降低网络开关板上的高速信号的跟踪长度和插入损耗

    公开(公告)号：US20160183402A1

    公开(公告)日：2016-06-23

    申请号：US14581962

    申请日：2014-12-23

    Applicant: Intel Corporation

    Inventor： Vladimir Tamarkin ,  William F. Federer ,  Thomas W. Genetti

    IPC: H05K7/14 ,  H04L12/935

    CPC classification number: H04L49/30 ,  H05K1/117 ,  H05K2201/0784 ,  H05K2201/09163 ,  H05K2201/09227

    Abstract: An electrical device can include a printed circuit board (PCB), an electrical component integrated therewith, and connectors that are each integrated with a certain edge of the PCB. Traces can provide electrical channels between the connectors and the electrical component. Some of the connectors can be integrated at a first edge of the PCB and within a first plane, and other connectors can be integrated at a second edge of the PCB and within a second plane that is distinct from the first plane.

    Abstract translation: 电气设备可以包括印刷电路板（PCB），与其集成的电气部件，以及每个与PCB的某一边缘集成的连接器。 轨迹可以在连接器和电气部件之间提供电气通道。 一些连接器可以集成在PCB的第一边缘处并在第一平面内，并且其它连接器可以集成在PCB的第二边缘处并且在与第一平面不同的第二平面内。

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