公开(公告)号：JPH06282453A

公开(公告)日：1994-10-07

申请号：JP29034193

申请日：1993-11-19

Applicant: ADVANCED MICRO DEVICES INC

Inventor： GOPI GANAPASHII ,  TSUAN TORAN

IPC: G06F11/22 ,  G11C29/36 ,  G11C29/40 ,  G11C29/44

Abstract: PURPOSE: To provide the mechanism and method for testing a known error place in an embedded array with a series of predetermined test patterns. CONSTITUTION: The said mechanism includes a determinative test pattern generator 14 which sends a test pattern to the array 12. The pattern is previously selected according to the fault trend of the array 12. The contents of the array 12 are read out and compared with the test pattern to generate a current error term. The current error term is compressed by a register 16 through logical operation and it saves an error display. The contents of the register 12 constitute a cumulative error term and can be read out to judge whether an error occurs or not. Respective columns of the tested array 12 correspond to bit positions in the cumulative error term and a user can judge which column in the array 12 causes the error.

公开(公告)号：JPH06261102A

公开(公告)日：1994-09-16

申请号：JP29980093

申请日：1993-11-30

Applicant: ADVANCED MICRO DEVICES INC

Inventor： IAN ESU KUREIFUOODO ,  UIRIAMU ROO ,  NADAA BIJIE

IPC: H04L29/10 ,  H04L12/46 ,  H04L13/08

Abstract: PURPOSE: To provide the system which monitors the source address of an incoming packet on a repeater and compares it with an internally stored value. CONSTITUTION: This is a system used for a network and a system which authenticates a data packet, gives safety for securely preventing unauthenticated data from being received, performs improved monitoring of data packets sent and received through the network, and detects changes of the network topology. The repeater used for this system provides improved features by giving detecting and interpreting capability for packet data, and a source address(AS), a destination address(DA), and a field.

公开(公告)号：JPH06259981A

公开(公告)日：1994-09-16

申请号：JP26323693

申请日：1993-10-21

Applicant: ADVANCED MICRO DEVICES INC

Inventor： MAIKERU EI BAN BASUKAAKU ,  JIYONII CHIYANNRII CHIEN ,  CHIYUN KEI CHIYAN ,  RII II KURIIBURANDO ,  ANTONIO MONTARUBO

IPC: G11C17/00 ,  G11C16/06 ,  G11C16/30 ,  H02M3/07 ,  H03K19/096

Abstract: PURPOSE: To provide a drain power source which generates an adjusted positive potential during programming and gives it to the drain area of a selected memory cell through a bit line of an array of a Flash EEPROM memory cells. CONSTITUTION: The drain power source includes a charge pump means 20 which consists of a plurality of charge pump parts 20a to 20h driven by a plurality of alternating clock signals and properly generates a positive voltage in the high level. Canceling means 26 and 28 are connected to respective charge pump parts to effectively cancel the threshold voltage drop in the charge pump circuit. An adjuster circuit 22 responding to the adjusted positive potential in an output node and a reference voltage is given to generated a control voltage, and the positive voltage in the high level on the output node is controlled.

公开(公告)号：JPH06237285A

公开(公告)日：1994-08-23

申请号：JP31772093

申请日：1993-12-17

Applicant: ADVANCED MICRO DEVICES INC

Inventor： DEIRU II GURITSUKU

IPC: G06F13/00 ,  H04L13/08 ,  H04L29/02 ,  H04L29/06 ,  H04L29/08

Abstract: PURPOSE: To obtain a receiver of a high level data link controller by perfoming flag and aboard detection, an intra-frame, external determination, zero elimination and several high level control functions with a signal logic device. CONSTITUTION: A receiving FIFO buffer 49 contains a buffer of two word depth which connects a 8-bit shift register 46 to a data bus that includes a microprocessor interface. Each word, that is stored in the buffer 49 includes eight data bits and three state bits. That is, it includes FIFO location Fu 11 bits, CRC(cyclic redundancy check) bits and EOM(end-of-message) bits. Although each byte is loaded by the FIFO 49 when it is received by an HDLC receiver 40, it does not proceed until the next byte or an end flag is detected. A full bit and the EOM bit are set together when the end flag is detected, and when the CRC does not detects them, a CRC bit is invalidly set. When a state bit is set, a byte proceeds.

公开(公告)号：JPH06216728A

公开(公告)日：1994-08-05

申请号：JP27426093

申请日：1993-11-02

Applicant: ADVANCED MICRO DEVICES INC

Inventor： HERUMAN EMU CHIYAN ,  BURATSUDORII SHIYAAPEEGAISURAA

IPC: H03K5/13 ,  G11C7/24 ,  G11C16/22 ,  H03K19/003 ,  H03K19/173 ,  H03K19/177

Abstract: PURPOSE: To protect a programmable logic device from an unwanted input overshoot voltage by activating the editing mode of logic device only when inputting an overvoltage during the duration longer than predetermined time delay. CONSTITUTION: When the overvoltage is detected at the input of circuit 10, a circuit 20 activates a time delay circuit 30. When the time impressing the overvoltage to the input of circuit 10 is longer than the predetermined time constant of time delay circuit 30, that overvoltage can be considered as a desired program voltage, and the editing mode of logic device is activated. In this case, the time delay of circuit 30 is determined by the strength of P channel transistor directly related with the turn-on resistance of P channel transistor and the size of capacitor.

公开(公告)号：JPH06204918A

公开(公告)日：1994-07-22

申请号：JP26869593

申请日：1993-10-27

Applicant: ADVANCED MICRO DEVICES INC

Inventor： HAABAATO EMU CHIEN ,  BUI BIHAYAKUMARAN NAIIRU

IPC: H04B3/23

Abstract: PURPOSE: To eliminate the need for a double talker detector by stopping the adaptation of a balanced filter in making a correlation value non-correlational by means of an α-signal, when the correlation value detected during an adaptive process becomes smaller than a certain threshold value and restarting the adaptation until the correlation value again becomes smaller than the threshold value, when the detected correlation value is larger than the threshold value. CONSTITUTION: A non-correlation controller 48 controls a adaptive balanced filter 40 of an echo controller 16 by detecting a cross-correlation between a far-end signal and a residual echo. The controller 48 inputs two signals of a signal from a gain reception controller 32 and the residual echo of a BPF 18. When a correlation value, detected during an adaptive process, becomes smaller than a certain threshold, the controller 48 stops the adaptation of the filter 40 by using an α-signal, which makes the correlation value noncorrelative. When the detected correlation value becomes larger than the threshold, the controller 48 restarts the adaptation, until the correlation value again becomes larger than the threshold. The controller 48 does not rely upon the level of a near-end talker signal, so long as the near-end signal is non-correlational with the far-end signal.

公开(公告)号：JPH06204842A

公开(公告)日：1994-07-22

申请号：JP17398993

申请日：1993-07-14

Applicant: ADVANCED MICRO DEVICES INC

Inventor： AN KEI UU

IPC: H03K19/0175 ,  H03K19/0185 ,  H03M5/14 ,  H03K5/13

Abstract: PURPOSE: To provide a logic interface circuit which restores phase and data information from differential input signals, having distorted duty cycles generated by ECL(emitter coupled logic)-CMOS translators. CONSTITUTION: A logical interface circuit incorporates first and second ECL- CMOS translators T1 and T2, first and second delay circuits, and an output logic circuit. The first delay circuit incorporates a first inverter I1, a first delay network D1, and a first NAND logical gate N1 and the second delay circuit incorporates a second inverter 12, a second delay network D2, and a second NAND logical gate N2. The output logic circuit incorporates a third NAND logical gate. The interface circuit generates an output signal, the cycle time of which can be detected for defining frequency information and which has the shape of a pulse train, in which the presence/absence of pulses can be detected for defining data information.

公开(公告)号：JPH06204205A

公开(公告)日：1994-07-22

申请号：JP22237893

申请日：1993-09-07

Applicant: ADVANCED MICRO DEVICES INC

Inventor： HENRII JIMU FURUFUOODO JIYUNIA ,  MAAKU AI GAADONAA

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/762

Abstract: PURPOSE: To provide a method of avoiding overetching, which is performed on the surface part of a semiconductor material main body. CONSTITUTION: Oxide films 14 and 12 are removed from the surface of a semiconductor material main body, which has the thick oxide film 14 and the thin oxide film 12 adjacent to the film 14, without performing overetching on the surface of the main body. Therefore, a method for avoiding the deterioration of the surface of the main body is disclosed. First, a photoresist layer 113 is deposited on the film 12 in such a way as to cover the film 12, then, the film 14 is left as one part of the film 14 is left and etched during a certain period in such a way that the thickness of the film 14 corresponds to that of the film 12. Then, the layer 113 covering the film 12 is removed without performing considerably etching on any of the residual part 115 of the film 14 and the film 12. Lastly, the film 12 and the residual part 115 of the film 14 can be removed without performing excessively overetching on the surface of the main body.

公开(公告)号：JPH06204203A

公开(公告)日：1994-07-22

申请号：JP22094693

申请日：1993-09-06

Applicant: ADVANCED MICRO DEVICES INC

Inventor： SUTEIIBUN SHII HOORU ,  MAAKU AI GAADONAA ,  HENRII JIMU FURUFUOODO JIYUNIA

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/762

Abstract: PURPOSE: To provide a method of avoiding an excess overetching, which is performed on the surface part of a semiconductor material main body. CONSTITUTION: Oxide films 14 and 12 are removed from the surface of a semiconductor material main body, which has the thick oxide film 14 and the thin oxide film 12 covered with a nitride film adjacent to the film 14, without performing an excess overetching on the surface of the main body. Therefore, a method for avoiding the deterioration of the surface of the main body is disclosed. First, the film 14 is left as one part of the film 14 is left and is etched during a certain period in such a way that the thickness of the film 14 corresponds to that of the film 12. Then, the nitride film 10 covering the film 12 is removed without performing considerably an etching on any of the residual part 115 of the film 14 and the film 12. Lastly, the film 12 and the residual part 115 of the film 14 can be removed from the surface of the main body without performing excessively the overetching on the surface of the main body.

公开(公告)号：JPH06188725A

公开(公告)日：1994-07-08

申请号：JP19136193

申请日：1993-08-02

Applicant: ADVANCED MICRO DEVICES INC

Inventor： OMU PII AGURAWARU

IPC: H03K19/173 ,  H03K19/177

Abstract: PURPOSE: To provide an architecture used for a PLD(programmable logical device) which can perform the proportional reduction from low density to very high density. CONSTITUTION: Two or more PLB(programmable logical block) 201A are connected to each other via a programmable switch matrix including a programmable input switch matrix 220A and an integrated programmable switch matrix 230. Each PLB is connected to plural programmable I/O macro cells 203A via an output switch matrix 240A, and each cell 203A is connected to one of I/O pins 205A. The matrix 220A evenly processes all feedback signals to be supplied to the matrix 230, simplifies the designation of a signal path and improves the function performance and the resources contained in the PLD.