公开(公告)号：US20230068461A1

公开(公告)日：2023-03-02

申请号：US17812549

申请日：2022-07-14

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Xiaoguang Wang ,  Dinggui Zeng ,  Huihui Li ,  Kanyu Cao

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L23/528 ,  H01L29/423 ,  H01L29/786

Abstract: Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof, and a memory. The semiconductor structure may at least include: a plurality of transistors arranged in a staggered manner, wherein the transistors share one source plate, a channel of the transistor is located on the source plate, and a channel length direction of the transistor is perpendicular to a surface of the source plate, and a material of the channel includes an oxide semiconductor; a plurality of drain contact members, electrically connected to drains of the transistors, wherein an odd number of transistors share one drain contact member, and the transistors sharing the same drain contact member are driven by a same word line; and a plurality of magnetic tunnel junctions, located on the drain contact members, wherein the magnetic tunnel junctions are electrically connected to the drain contact members in a one-to-one corresponding manner.

公开(公告)号：US20230067509A1

公开(公告)日：2023-03-02

申请号：US17808382

申请日：2022-06-23

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Xiaoguang Wang ,  Dinggui Zeng ,  Huihui Li ,  Kanyu Cao

IPC: H01L27/22 ,  H01L29/786 ,  H01L43/12 ,  H01L29/66

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate. A plurality of vertical transistors arranged in an aligned manner are formed on the substrate, wherein a channel material of the vertical transistor includes an oxide semiconductor. A plurality of staggered contact pads connected to upper ends of the vertical transistors are formed on the vertical transistors, wherein a single contact pad is connected to the upper ends of an even number of vertical transistors. A magnetic tunnel junction is formed on the contact pad.

公开(公告)号：US20230065326A1

公开(公告)日：2023-03-02

申请号：US17808396

申请日：2022-06-23

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Xiaoguang WANG ,  Dinggui Zeng ,  Huihui Li ,  Kanyu Cao

IPC: H01L27/22 ,  H01L29/786

Abstract: The present application relates to a memory device and a preparing method thereof. The memory device includes: a substrate, and a plurality of memory cells disposed in an array on the substrate. Memory cells in adjacent rows are staggered in a row direction, and a distance between two adjacent memory cells in any row is a first distance. Memory cells in adjacent columns are staggered in a column direction, and a staggered distance is less than the first distance.

公开(公告)号：US20220393034A1

公开(公告)日：2022-12-08

申请号：US17805575

申请日：2022-06-06

Applicant: Beijing Superstring Academy of Memory Technology ,  Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L29/786 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

Abstract: A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.

公开(公告)号：US20250126776A1

公开(公告)日：2025-04-17

申请号：US18692472

申请日：2023-06-16

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Libin Jia ,  Yanlei Ping ,  Chao Tian

IPC: H10B12/00 ,  H01L21/223 ,  H01L21/768 ,  H10D84/01

Abstract: Disclosed are a semiconductor device, a manufacturing method therefor, and an electronic equipment, the semiconductor device includes: at least one vertical channel transistor disposed on a base substrate, and a bit line; the transistor includes a semiconductor pillar extending along a direction perpendicular to the base substrate, the semiconductor pillar includes a channel region, and a first region and a second region respectively disposed on two sides of the channel region, the second region is disposed between the base substrate and the first region, the bit line is in contact with the second region, and a plasma dopant concentration of a contact surface between the second region and the bit line is greater than or equal to 1e14 atoms/square centimeter.

公开(公告)号：US12262523B2

公开(公告)日：2025-03-25

申请号：US17818537

申请日：2022-08-09

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Deyuan Xiao ,  Yong Yu ,  Guangsu Shao

IPC: H10B12/00

Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure. The manufacturing method of a semiconductor structure includes: providing a substrate; forming a plurality of silicon pillars on the substrate, where the silicon pillars are arranged as an array; preprocessing the silicon pillar to form an active pillar, where the active pillar includes a first segment, a second segment, and a third segment; forming a first gate oxide layer on sidewalls of the second segment and the third segment; and forming a second gate oxide layer on the first gate oxide layer, where a length of the second gate oxide layer is less than that of the first gate oxide layer, and a thickness of the second gate oxide layer is greater than that of the first gate oxide layer.

公开(公告)号：US12250831B2

公开(公告)日：2025-03-11

申请号：US17805575

申请日：2022-06-06

Applicant: Beijing Superstring Academy of Memory Technology ,  Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu

IPC: H01L29/786 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H10D30/01 ,  H10D30/67

Abstract: A semiconductor device and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device includes: an active region, on a substrate, extending substantially in a vertical direction; a gate stack formed around at least a part of a periphery of the active region, the active region including a channel region opposite to the gate stack, and a first source/drain region and a second source/drain region, and the gate stack including a gate dielectric layer, a work function tuning layer and a gate electrode material layer, and the work function tuning layer being between the gate electrode material layer and the channel region; and a first low-k dielectric layer extending from a first end of the work function tuning layer to surround a first corner of an end portion, on a side facing the channel region, of the gate electrode material layer.

公开(公告)号：US20250081524A1

公开(公告)日：2025-03-06

申请号：US18260320

申请日：2021-12-24

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Ziyi LIU ,  Huilong ZHU

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device and a method for manufacturing the same. A substrate is provided. A first source-drain layer, a channel layer, and a second source-drain layer are sequentially stacked on the substrate. Both a gate dielectric layer and a gate structure surround the channel layer laterally. The gate structure includes a first portion extending laterally and a second portion extending upward from a periphery of the first portion. A second portion is located at a periphery of the second source-drain layer. A spacer layer is formed at an outer sidewall of the gate structure. The gate structure is etched to reduce a thickness of the gate structure. A sacrificial structure covering the gate structure is formed, and a capping layer covering the second source-drain layer, the sacrificial structure, and the spacer layer is formed. Thereby, the sacrificial structure is located at the periphery of the second source-drain layer and enclosed by the spacer layer. The capping layer is etched to obtain a first contact hole reaching the sacrificial structure. The sacrificial structure at the bottom of the first contact hole is removed to form a gap under the first contact hole. A first contact structure is formed in the first contact hole and the gap. Self-alignment between a bottom of the first contact structure and the gate structure is achieved, and the device has higher reliability.

公开(公告)号：US20250063714A1

公开(公告)日：2025-02-20

申请号：US18714798

申请日：2022-12-20

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Zhengyong ZHU ,  Chao ZHAO ,  Bokmoon KANG ,  Guilei WANG

IPC: H10B12/00 ,  H01L27/088 ,  H01L29/786

Abstract: Provided is a memory. The memory includes: a plurality of memory cells, word lines, and bit lines; wherein each of the memory cells comprises: a first transistor, wherein a first source of the first transistor is electrically connected to the bit line; a second transistor, connected in series to the first transistor; and a capacitor, electrically connected to a second drain of the second transistor. The first transistor and the second transistor are both n-type transistors or p-type transistors, and a first gate of the first transistor and a second gate of the second transistor are electrically connected to the word line.

公开(公告)号：US20250056790A1

公开(公告)日：2025-02-13

申请号：US18754418

申请日：2024-06-26

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Wenhua GUI ,  Xuezheng AI ,  Guilei WANG ,  Jin DAI ,  Xiangsheng WANG

IPC: H10B12/00

Abstract: Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.