公开(公告)号：DE69032655T2

公开(公告)日：1999-02-11

申请号：DE69032655

申请日：1990-10-24

Applicant: COMPAQ COMPUTER CORP

Inventor： MAYER DAVID J ,  CULLEY PAUL R ,  TAYLOR MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: A computer system has a processor (20) coupled to a cache controller (24), uses page mode memory devices (58) sand performs page hit detection (43) on the processor local bus (26). Column address and data values are latched by a memory controller (62) on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.

公开(公告)号：DE69130086T2

公开(公告)日：1999-01-21

申请号：DE69130086

申请日：1991-06-14

Applicant: COMPAQ COMPUTER CORP

Inventor： TIPLEY ROGER E

IPC: G06F12/08

Abstract: A method for achieving multilevel inclusion in a computer system with first and second level caches. The caches align themselves on a "way" basis by their respective cache controllers communicating with each other as to which blocks of data they are replacing and which of their cache ways are being filled with data. On first and second level cache read misses the first level cache controller provides way information to the second level cache controller to allow received data to be placed in the same way. On first level cache read misses and second level cache read hits, the second level cache controller provides way information the first level cache controller, which ignores its replacement indication and places data in the indicated way. On processor writes the first level cache controller caches the writes and provides the way information to the second level cache controller which also caches the writes and uses the way information to select the proper way for data storage. An inclusion bit is set on data in the second level cache that is duplicated in the first level cache. Multilevel inclusion allows the second level cache controller to perform the principal snooping responsibilities for both caches, thereby enabling the first level cache controller to avoid snooping duties until a first level cache snoop hit occurs. On a second level cache snoop hit, the second level cache controller checks the respective inclusion bit to determine if a copy of this data also resides in the first level cache. The first level cache controller is directed to snoop the bus only if the respective inclusion bit is set.

公开(公告)号：DE69322320D1

公开(公告)日：1999-01-14

申请号：DE69322320

申请日：1993-01-20

Applicant: COMPAQ COMPUTER CORP

Inventor： HESS RANDALL ,  COOPER PATRICK ,  INTERIANO ARMANDO ,  FREIMAN JOSEPH

IPC: G01R31/00 ,  G01R31/36 ,  H02J7/00

Abstract: A battery charge controller and fuel gauge which accurately monitors the voltage, temperature, and charge and discharge current of a rechargeable battery, and calculates the battery's charge capacity and charge level. Each time the battery is fully discharged, any calculated charge level remaining is divided by two and subtracted from the previously calculated charge capacity. When the battery is fully charged, the charge level is set equal to the charge capacity. During subsequent charge and discharge, the current is converted to a coulomb count and added or subtracted from the charge level to maintain an accurate charge level. Fast charge inefficiency due to temperature is considered by subtracting a temperature proportional factor before the charge level of the battery is updated. The charge level, voltage and temperature are used to determine the optimal fast charge termination point to achieve full charge and prevent temperature abuse and overcharge. A fast charge is applied only if the battery is within proper voltage and temperature ranges. The charge controller includes a microcontroller circuit within the same battery pack as the battery, which is powered by the battery when AC power is unavailable. The microcontroller circuit consumes very little power, measures circuit errors to assure data accuracy, times periods of self-discharge and updates the charge level accordingly. The microcontroller circuit also includes memory to store the battery charge information and a communication port to provide the charge information to a computer system connected to the battery pack.

公开(公告)号：DE69032655D1

公开(公告)日：1998-10-22

申请号：DE69032655

申请日：1990-10-24

Applicant: COMPAQ COMPUTER CORP

Inventor： MAYER DAVID J ,  CULLEY PAUL R ,  TAYLOR MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: A computer system has a processor (20) coupled to a cache controller (24), uses page mode memory devices (58) sand performs page hit detection (43) on the processor local bus (26). Column address and data values are latched by a memory controller (62) on memory write operations to allow early completion of the cycle so that the next cycle can partially overlap. This allows the use of economical memories and yet have zero wait state page hit operation.

公开(公告)号：DE69130086D1

公开(公告)日：1998-10-08

申请号：DE69130086

申请日：1991-06-14

Applicant: COMPAQ COMPUTER CORP

Inventor： TIPLEY ROGER E

IPC: G06F12/08

Abstract: A method for achieving multilevel inclusion in a computer system with first and second level caches. The caches align themselves on a "way" basis by their respective cache controllers communicating with each other as to which blocks of data they are replacing and which of their cache ways are being filled with data. On first and second level cache read misses the first level cache controller provides way information to the second level cache controller to allow received data to be placed in the same way. On first level cache read misses and second level cache read hits, the second level cache controller provides way information the first level cache controller, which ignores its replacement indication and places data in the indicated way. On processor writes the first level cache controller caches the writes and provides the way information to the second level cache controller which also caches the writes and uses the way information to select the proper way for data storage. An inclusion bit is set on data in the second level cache that is duplicated in the first level cache. Multilevel inclusion allows the second level cache controller to perform the principal snooping responsibilities for both caches, thereby enabling the first level cache controller to avoid snooping duties until a first level cache snoop hit occurs. On a second level cache snoop hit, the second level cache controller checks the respective inclusion bit to determine if a copy of this data also resides in the first level cache. The first level cache controller is directed to snoop the bus only if the respective inclusion bit is set.

公开(公告)号：SG53137A1

公开(公告)日：1998-09-28

申请号：SG1997004511

申请日：1997-12-17

Applicant: COMPAQ COMPUTER CORP

Inventor： TRAN HUYAN B ,  CASTELL ROBIN T

IPC: G06F1/16 ,  H04M11/00 ,  H04M11/06 ,  G06F1/12

Abstract: A laptop computer contains a built-in modem and has a phone jack for connection to a telephone line while the computer is being operated in a stand-alone mode. A docking station into which the laptop computer may be docked allows the combined unit to be operated in a desk-top mode. The docking station may have a full-sized keyboard and display so that the laptop functions as the main computer a user may employ in the office or home. A telephone connection is already in place at the docking station so that the user need not make a phone line connection to invoke the docked mode, but instead merely nests the laptop in the docking station. In one embodiment, the only components of the modem that are duplicated in the docking station are the phone jack itself and an isolation and 2-to-4 wire converter, so the plug-in connector ordinarily employed between a laptop and a docking station may be of a low-voltage, spike voltage protected form, whereby the coupling used for computer logic and control levels is compatible. The possibility of damage to computer circuits due to the proximity of high-voltage telephone line connections is thus avoided.

公开(公告)号：SG53119A1

公开(公告)日：1998-09-28

申请号：SG1997003956

申请日：1997-11-05

Applicant: COMPAQ COMPUTER CORP

Inventor： KNOX RICHARD M ,  WALKER DALE S ,  MERCER WILLIAM BURTON

IPC: G02F1/13 ,  F21V9/00 ,  F21V9/04 ,  F21V9/14 ,  F21V13/04 ,  G02B27/28 ,  G03B21/00 ,  G03B21/14 ,  G09F9/00 ,  H01J61/02 ,  H01J61/12 ,  H01J61/34 ,  H01J61/40 ,  H01J65/00 ,  H01J65/04 ,  H04N5/74 ,  H04N9/31 ,  H01J61/38

Abstract: An electrodeless lamp apparatus of high efficiency employs a reflection system that allows the lamp to reabsorb light energy. The energy is redirected back to the light to provide increased system efficiency. The redirected light is of the wrong polarization and/or wrong parts of the color spectrum. The lamp efficiency is increased because of the optical pumping as well as the reuse (after some downshifting) of the returned light. In one embodiment, a projection system provides an image source or projection engine that includes the improved high efficiency lamp of the present invention.

公开(公告)号：SG53011A1

公开(公告)日：1998-09-28

申请号：SG1997002413

申请日：1997-07-09

Applicant: COMPAQ COMPUTER CORP

Inventor： HALLOWELL WILLIAM C ,  FRITZ BRIAN C

IPC: G06F1/30 ,  G06F9/445 ,  G06F11/14 ,  G06F1/32 ,  G06F12/16

公开(公告)号：AT170801T

公开(公告)日：1998-09-15

申请号：AT93916839

申请日：1993-06-29

Applicant: COMPAQ COMPUTER CORP

Inventor： GOOD LOWELL M

IPC: B41J2/045 ,  B41J2/055 ,  B41J2/155 ,  B41J2/16

公开(公告)号：AU696171B2

公开(公告)日：1998-09-03

申请号：AU3293795

申请日：1995-09-27

Applicant: COMPAQ COMPUTER CORP

Inventor： MURPHY RICHARD D

IPC: B41J2/045 ,  B41J2/055 ,  B41J2/14 ,  B41J2/155 ,  B41J2/16

Abstract: A page wide piezoelectric ink jet print engine and a method of manufacturing the same. The page wide ink jet print engine includes lower and upper body parts, each formed from piezoelectric material and having a plurality of generally parallel, spaced projections. Lower side surfaces of the projections of the lower body part are conductively mounted to corresponding bottom side surfaces of the projections of the upper body part to define a plurality of generally parallel, axially extending ink-carrying channels from which ink may be ejected. The lower and upper body parts are then circumferentially poled such that, for the lower body part, first and second polarization fields respectively extend between the top side surface of each one of the projections and top side surfaces of first and second projections adjacent thereto and, for the upper body part first and second polarization fields respectively extend between the bottom side surface of each one of the projections and bottom side surfaces of first and second projections adjacent thereto. By applying voltage to selective ones of the projections, the channels may be selectively expanded to draw ink from an associated ink delivery system and compressed to cause the ejection of a droplet of ink therefrom.