公开(公告)号：EP1887623A3

公开(公告)日：2009-09-09

申请号：EP07113383.9

申请日：2007-07-28

Applicant: Fujitsu Microelectronics Limited

Inventor： TANAKA, Takuji

IPC: H01L27/02 ,  H01L27/11

CPC classification number: H01L27/1104 ,  H01L27/0203 ,  H01L27/11

Abstract: Disclosed is a semiconductor memory device capable of realizing reduction in an SRAM unit cell area. Using as a standard configuration a parallel-type SRAM unit cell having each pair of load transistors (L1,L2), driver transistors (D1,D2) and transfer transistors (T1,T2), all or a part of the gate electrodes (51-54) and active regions (55-58) configuring at least any one of the pairs of the transistors, for example, the pair of the transfer transistors (T1,T2) are configured obliquely in a predetermined direction from the standard configuration. As a result, a size in a cell outside part including the driver transistor and the transfer transistor is reduced. At the same time, a distance between the load transistors in the central part is reduced as compared with that in the standard configuration. Thus, area reduction in the whole SRAM unit cell is realized.

公开(公告)号：EP1528593B1

公开(公告)日：2009-07-22

申请号：EP02758823.5

申请日：2002-08-09

Applicant: Fujitsu Microelectronics Limited

Inventor： AIBA, Kazuyuki ,  TAKASHIMA, Akira ,  OZAWA, Kaname ,  HIRAOKA, Tetsuya ,  SUZUKI, Takaaki ,  MATSUZAKI, Yasurou

IPC: H01L21/60

CPC classification number: H01L29/0657 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511

Abstract: A semiconductor chip is secured in a state deformed into a substantially cylinder shape by a coating material formed on its surface. The deformed semiconductor chip is flip-chip connected to an interposer and sealed with sealing resin onto the interposer. Solder balls are provided, as external terminals, on the other side of the interposer.

Abstract translation: 通过形成在其表面上的涂层材料将半导体芯片固定在变形为大致圆柱形状的状态中。 将变形的半导体芯片倒装连接到插入器并用密封树脂密封到插入器上。 在插入器的另一侧上提供焊球作为外部端子。

公开(公告)号：EP1763238A3

公开(公告)日：2009-07-15

申请号：EP06250838.7

申请日：2006-02-16

Applicant: Fujitsu Microelectronics Limited

Inventor： Iga. Kiichiro

IPC: H04N5/77

CPC classification number: H04N21/242 ,  H04N19/60 ,  H04N21/23406

Abstract: An image processor for lowering data transfer speed. A JPEG compression circuit (34) performs two-dimensional compression process on data (S1) output from a YCbCr conversion circuit (31) to generate compressed image data (S3). A timing signal generator (37) changes the frequency of a transfer clock signal (TCK) in accordance with the compressed image data (S3). An output circuit (36) outputs the compressed image data (ED) in accordance with the transfer clock signal (TCK).

公开(公告)号：EP1361580B1

公开(公告)日：2009-07-01

申请号：EP03016398.4

申请日：2000-09-27

Applicant: Fujitsu Microelectronics Limited

Inventor： Fujioka, Shinya, c/o Fujitsu Limited ,  Kawakubo, Tomohiro, c/o Fujitsu Limited ,  Nishimura, Koichi, c/o Fujitsu Limited ,  Sato, Kotoku, c/o Fujitsu Limited

IPC: G11C5/14 ,  G11C11/406

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/406 ,  G11C2207/2227

公开(公告)号：EP2058850A3

公开(公告)日：2009-06-03

申请号：EP09151138.6

申请日：2002-03-21

Applicant: Fujitsu Microelectronics Limited

Inventor： Teshirogi, Kazuo ,  Shimobeppu, Yuzo ,  Yoshimoto, Kazuhiro ,  Watanabe, Mitsuhisa ,  Shinjo, Yoshiaki ,  Yoshida, Eiji ,  Hayasaka, Noboru

IPC: H01L21/68

CPC classification number: H01L21/67092 ,  B24B37/042 ,  B32B37/003 ,  B32B37/1018 ,  B32B38/0012 ,  B32B2310/0831 ,  B32B2457/14 ,  H01L21/304 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/6838 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  Y10T29/5313 ,  Y10T29/53191 ,  Y10T428/1452 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A semiconductor substrate jig used for arranging a film on a semiconductor substrate, wherein said semiconductor substrate jig comprises a frame with a bottom, a set of plural annular members arranged concentrically within said frame and constructed so as to be individually movable in a direction perpendicular to said semiconductor substrate, wherein heights of said annular members in said direction perpendicular to said semiconductor substrate gradually increase from an outer circumference toward an inner circumference, a biasing member for biasing each of said annular members toward said bottom of said frame, and an operating member contacting said annular members by operating movement in said frame and provided for biasing in a direction separating said annular members from said bottom of said frame, against bias force of said biasing member. Each of said annular members is movable so as to gradually press and move said film arranged between said semiconductor substrate and said set of annular members toward said semiconductor substrate from center outward with said operating movement of said operating member.

公开(公告)号：EP1100089B1

公开(公告)日：2009-05-27

申请号：EP00308482.9

申请日：2000-09-27

Applicant: Fujitsu Microelectronics Limited

Inventor： Fujioka, Shinya ,  Kawakubo, Tomohiro ,  Nishimura, Koichi ,  Sato, Kotoku

IPC: G11C5/14

CPC classification number: G11C5/14 ,  G11C5/147 ,  G11C11/406 ,  G11C2207/2227

公开(公告)号：EP1600979B1

公开(公告)日：2009-05-20

申请号：EP04030747.2

申请日：2004-12-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Yoshioka, Hiroshi ,  Takeshima, Toru

IPC: G11C11/22

CPC classification number: G11C11/22

公开(公告)号：EP2058853A1

公开(公告)日：2009-05-13

申请号：EP09151140.2

申请日：2002-03-21

Applicant: Fujitsu Microelectronics Limited

Inventor： Teshirogi, Kazuo ,  Shimobeppu, Yuzo ,  Yoshimoto, Kazuhiro ,  Watanabe, Mitsuhisa ,  Shinjo, Yoshiaki ,  Yoshida, Eiji ,  Hayasaka, Noboru

IPC: H01L21/683 ,  H01L21/687 ,  H01L21/68

CPC classification number: H01L21/67092 ,  B24B37/042 ,  B32B37/003 ,  B32B37/1018 ,  B32B38/0012 ,  B32B2310/0831 ,  B32B2457/14 ,  H01L21/304 ,  H01L21/67132 ,  H01L21/6836 ,  H01L21/6838 ,  H01L21/78 ,  H01L24/27 ,  H01L24/29 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/07802 ,  Y10T29/5313 ,  Y10T29/53191 ,  Y10T428/1452 ,  H01L2924/3512 ,  H01L2924/00

Abstract: A semiconductor substrate jig comprises: a first jig having a first suction mechanism sucking said semiconductor substrate and a second jig having a second suction mechanism sucking said semiconductor substrate, said first and second jigs being removably constructed and independently sucking said semiconductor substrate.

Abstract translation: 半导体衬底夹具包括：第一夹具，其具有吸入所述半导体衬底的第一抽吸机构和具有吸入所述半导体衬底的第二抽吸机构的第二夹具，所述第一和第二夹具可移除地构造并独立地吸取所述半导体衬底。

公开(公告)号：EP1615142A3

公开(公告)日：2009-04-22

申请号：EP05250189.7

申请日：2005-01-14

Applicant: Fujitsu Microelectronics Limited

Inventor： Kasama, Ichiro, c/o Fujitsu Limited ,  Suzuki, Toshiaki, c/o Fujitsu Limited ,  Kawano, Tetsuo, c/o Fujitsu Limited ,  Imafuku, Kazuaki, c/o Fujitsu Limited ,  Furukawa, Hiroshi, c/o Fujitsu Limited

IPC: G06F15/76

CPC classification number: G06F9/461 ,  G06F9/3885 ,  G06F9/3897

Abstract: A reconfigurable processor in which an application can be switched more freely. A switching condition associating section (2) associates output from a plurality of arithmetic and logic unit modules (1a, b, c, d) used as switching conditions for switching the operation of an arithmetic and logic unit group with a plurality of states indicative of switching condition codes. When a switching condition code output section (3) decides that a switching condition comes into existence on the basis of the output from the plurality of arithmetic and logic unit modules set as the switching conditions, the switching condition code output section (3) outputs a switching condition code corresponding to the switching condition which comes into existence. When a sequencer accepts the switching condition code, the sequencer switches the arithmetic and logic unit group to a state corresponding to the switching condition code.

公开(公告)号：EP2043304A1

公开(公告)日：2009-04-01

申请号：EP08161499.2

申请日：2008-07-30

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Hideaki ,  Ogawa, Hitoshi

IPC: H04L12/40 ,  H04L29/06

CPC classification number: H04L12/40039 ,  H04L5/1438 ,  H04L12/4013 ,  Y02D50/10

Abstract: A transceiver that reduces power consumption when data is transferred between devices in different modes. The transceiver is arranged in a first node (6) and in a second node (9), which communicate between each other. A first control unit (12) generates a first signal transmitted from the first node in predetermined time intervals during a first period that establishes an environment for communication between the first node and the second node. The second node transmits a second signal transmitted in response to the first signal. The first control unit generates a third signal upon detection of the second signal. A second control unit (13) gradually decreases amplitude of the first signal based on the third signal to set the amplitude of the first signal to a predetermined amplitude so that the second node is receivable of the first signal.

Abstract translation: 一种收发器，可在不同模式的设备之间传输数据时降低功耗。 收发器布置在彼此通信的第一节点（6）和第二节点（9）中。 第一控制单元（12）在建立用于第一节点和第二节点之间的通信的环境的第一周期期间以预定时间间隔生成从第一节点发送的第一信号。 第二节点发送响应于第一信号而发送的第二信号。 第一控制单元在检测到第二信号时产生第三信号。 第二控制单元（13）基于第三信号逐渐降低第一信号的幅度，以将第一信号的幅度设置为预定幅度，使得第二节点可接收第一信号。