公开(公告)号：KR100467576B1

公开(公告)日：2005-01-24

申请号：KR1020010053270

申请日：2001-08-31

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  김만섭 ,  강동석

IPC: G06Q30/00

Abstract: PURPOSE: A method and a system for providing an electronic coupon are provided to make a customer and a member shop conveniently and effectively use the electronic coupon at selling, and to obtain marketing data by collecting use particulars of the electronic coupon. CONSTITUTION: An electronic coupon reader(2) includes a communication interface(21) for the communication with an electronic coupon publication server(1) transmitting the electronic coupon to a mobile communication terminal(3) of the customer, an RF(Radio Frequency) module(20) for the non-contact RF communication with the terminal(3), and a processor(22) transmitting an electronic coupon ID received from the terminal(3) to the server(1), requesting an approval and receiving a response from the server(1). The RF module(20) includes an RF block(203) transmitting/receiving a non-contact RF signal from the terminal(3) and a logic block(202) extracting the electronic coupon ID from the RF signal and transmitting the RF signal to the processor(22). The electronic coupon reader(1) includes a display, and the processor(22) displays the response for an approval request from the server(1).

Abstract translation: 目的：提供一种提供电子优惠券的方法和系统，以使顾客和会员商店在销售时方便和有效地使用电子优惠券，并通过收集电子优惠券的使用细节来获得市场数据。 一种电子优惠券阅读器（2），包括用于与电子优惠券发布服务器（1）通信的通信接口（21），该电子优惠券发布服务器（1）将电子优惠券发送给客户的移动通信终端（3），RF（射频） 用于与终端（3）进行非接触RF通信的模块（20），以及处理器（22），用于将从终端（3）接收的电子优惠券ID发送到服务器（1），请求批准并接收响应 从服务器（1）。 RF模块（20）包括从终端（3）发送/接收非接触RF信号的RF块（203）和从RF信号提取电子优惠券ID并将RF信号发送到 处理器（22）。 电子优惠券读取器（1）包括显示器，并且处理器（22）显示来自服务器（1）的针对批准请求的响应。

公开(公告)号：KR100454128B1

公开(公告)日：2004-10-26

申请号：KR1020020017949

申请日：2002-04-02

Applicant: 삼성전자주식회사

Inventor： 이수근 ,  정주혁 ,  김일구 ,  이경우 ,  박완재 ,  김재학

IPC: H01L21/28

CPC classification number: H01L21/76831 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76835 ,  H01L2221/1036

Abstract: Provided are an inter-metal dielectric pattern and a method of forming the same. The pattern includes a lower interconnection disposed on a semiconductor substrate, a lower dielectric layer having a via hole exposing the lower interconnection and covering the semiconductor substrate where the lower interconnection is disposed, and an upper dielectric pattern and a lower capping pattern, which include a trench line exposing the via hole and sequentially stacked on the lower dielectric layer. The lower dielectric layer and the upper dielectric pattern are low k-dielectric layers formed of materials such as SiO2, SiOF, SiOC, and porous dielectric. The method includes forming an inter-metal dielectric layer including a lower dielectric layer and upper dielectric layer, which are sequentially stacked, on a lower interconnection formed on a semiconductor substrate. The inter-metal dielectric layer is patterned to form a via hole, which exposes the upper side of the lower interconnection. Then, an upper capping layer is formed on the entire surface of the semiconductor substrate including the via hole. The upper capping layer and the upper dielectric layer are successively patterned to form a trench line exposing the upper side of the via hole. The upper capping layer is formed of at least one material selected from the group consisting of a silicon oxide layer, a silicon carbide layer, a silicon nitride layer, and a silicon oxynitride layer, by using PECVD.

Abstract translation: 提供了金属间介电图案及其形成方法。 该图案包括设置在半导体衬底上的下互连，具有暴露下互连并覆盖设置有下互连的半导体衬底的通孔的下介电层，以及包括下部电介质图案和下部图案的上部电介质图案和下部图案图案， 沟槽线暴露通孔并顺序地堆叠在下介电层上。 下电介质层和上电介质图案是由诸如SiO 2，SiOF，SiOC和多孔电介质的材料形成的低k电介质层。 该方法包括在形成于半导体衬底上的下互连上形成包括顺序堆叠的下介电层和上介电层的金属间介电层。 金属间介电层被图案化以形成暴露下互连的上侧的通孔。 然后，在包括通孔的半导体衬底的整个表面上形成上覆盖层。 上覆盖层和上介电层被连续图案化以形成暴露通孔上侧的沟槽线。 通过使用PECVD，上覆盖层由选自由氧化硅层，碳化硅层，氮化硅层和氮氧化硅层组成的组中的至少一种材料形成。

公开(公告)号：KR100432885B1

公开(公告)日：2004-05-22

申请号：KR1020020001470

申请日：2002-01-10

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  이수근 ,  박기관 ,  이경우

IPC: H01L21/3205

Abstract: PURPOSE: A method for forming an interlayer dielectric pattern is provided to be capable of finely forming an opening portion and securing the vertical profile of the opening portion by using a spacer as an etching mask and using an organic polymer layer as the interlayer dielectric. CONSTITUTION: After forming a conductive layer pattern(110) at the upper portion of a semiconductor substrate, an interlayer dielectric and a hard mask layer are sequentially deposited on the entire surface of the resultant structure. Then, a hard mask pattern having the first opening portion(171) is formed by selectively patterning the hard mask layer for exposing the upper surface of the interlayer dielectric. A spacer(190) is formed at both sidewalls of the first opening portion. The upper surface of the conductive layer pattern is exposed by selectively etching the resultant structure using the spacer as an etching mask. Preferably, the interlayer dielectric is made of at least one selected from a group consisting of an organic polymer layer, a fluorine doped oxide layer, a carbon doped oxide layer, and a silicon oxide layer.

Abstract translation: 目的：提供一种用于形成层间电介质图案的方法，其能够通过使用间隔物作为蚀刻掩模并使用有机聚合物层作为层间电介质来精细地形成开口部分并且确保开口部分的垂直轮廓。 构成：在半导体衬底的上部形成导电层图形（110）之后，在所得结构的整个表面上顺序沉积层间电介质和硬掩模层。 然后，通过选择性地图案化硬掩模层来形成具有第一开口部分（171）的硬掩模图案以暴露层间电介质的上表面。 间隔物（190）形成在第一开口部分的两个侧壁处。 通过使用隔离物作为蚀刻掩模选择性地蚀刻所得结构来暴露导电层图案的上表面。 优选地，层间电介质由选自由有机聚合物层，氟掺杂氧化物层，碳掺杂氧化物层和氧化硅层组成的组中的至少一种制成。

公开(公告)号：KR100416596B1

公开(公告)日：2004-02-05

申请号：KR1020010025573

申请日：2001-05-10

Applicant: 삼성전자주식회사

Inventor： 이수근 ,  신홍재 ,  이경우 ,  김재학

IPC: H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144

Abstract: A method of forming an interconnection line in a semiconductor device is provided. A first etching stopper is formed on a lower conductive layer which is formed on a semiconductor substrate. A first interlayer insulating layer is formed on the first etching stopper. A second etching stopper is formed on the first interlayer insulating layer. A second interlayer insulating layer is formed on the second etching stopper. The second interlayer insulating layer, the second etching stopper, and the first interlayer insulating layer are sequentially etched using the first etching stopper as an etching stopping point to form a via hole aligned with the lower conductive layer. A protective layer is formed to protect a portion of the first etching stopper exposed at the bottom of the via hole. A portion of the second interlayer insulating layer adjacent to the via hole is etched using the second etching stopper as an etching stopping point to form a trench connected to the via hole. The protective layer is removed. The portion of the first etching stopper positioned at the bottom of the via hole is removed. An upper conductive layer that fills the via hole and the trench and is electrically connected to the lower conductive layer is formed.

Abstract translation: 提供了一种在半导体器件中形成互连线的方法。 第一蚀刻停止层形成在形成于半导体衬底上的下导电层上。 在第一蚀刻阻挡层上形成第一层间绝缘层。 在第一层间绝缘层上形成第二蚀刻阻挡层。 在第二蚀刻阻挡层上形成第二层间绝缘层。 使用第一蚀刻停止层作为蚀刻停止点依次蚀刻第二层间绝缘层，第二蚀刻停止层和第一层间绝缘层，以形成与下部导电层对齐的过孔。 形成保护层以保护暴露在通孔底部的第一蚀刻阻挡层的一部分。 使用第二蚀刻停止层蚀刻与通孔相邻的第二层间绝缘层的一部分作为蚀刻停止点以形成连接到通孔的沟槽。 保护层被移除。 位于通孔底部的第一蚀刻停止层部分被去除。 形成填充通孔和沟槽并电连接到下导电层的上导电层。

公开(公告)号：KR1020020045494A

公开(公告)日：2002-06-19

申请号：KR1020010036933

申请日：2001-06-27

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  신홍재 ,  이수근 ,  이경우

IPC: H01L21/283

Abstract: PURPOSE: A method for forming a semiconductor device having low permittivity interlayer dielectric is provided to exactly form a micro pattern on a SiOC layer and to restrain a parasitic capacitance between interconnections or contact plugs by using the SiOC layer having a low dielectric constant. CONSTITUTION: A low permittivity carbon oxide silicon layer made of SiOC is formed on a substrate(100) by a CVD(Chemical Vapour Deposition) using a nitrogen included gas as a source gas or a carrier gas. A plasma processing is performed on the carbon oxide silicon layer by supplying gases, such as a helium, a hydrogen, an N2O, or an Ar gas to a processing chamber. A photoresist is deposited and patterned on the plasma processed carbon oxide silicon layer(111).

Abstract translation: 目的：提供一种形成具有低介电常数层间电介质的半导体器件的方法，以在SiOC层上精确地形成微图案，并通过使用具有低介电常数的SiOC层来抑制互连或接触插塞之间的寄生电容。 构成：使用含氮气体作为原料气体或载气，通过CVD（化学气相沉积）在基板（100）上形成由SiOC制成的低介电常数碳氧化硅层。 通过向处理室供给诸如氦气，氢气，N 2 O或Ar气体的气体，对碳氧化硅硅层进行等离子体处理。 在等离子体处理的碳氧化硅层（111）上沉积并图案化光致抗蚀剂。

公开(公告)号：KR1020020012106A

公开(公告)日：2002-02-15

申请号：KR1020000070973

申请日：2000-11-27

Applicant: 삼성전자주식회사

Inventor： 김원진 ,  이수근 ,  신홍재 ,  한재현 ,  김재학 ,  강호규

IPC: H01L21/28

Abstract: PURPOSE: A method for manufacturing an interconnection using a hydrogen silsesquioxane(HSQ) layer as an interlayer dielectric is provided to simplify a process for forming the interconnection, by performing a plasma treatment regarding the HSQ layer so that the HSQ layer is not damaged in a photolithography process to directly pattern the HSQ layer. CONSTITUTION: A low dielectric layer is formed on a semiconductor substrate(10). A plasma treatment process is performed regarding the entire surface of the low dielectric layer. The plasma-treated low dielectric layer is patterned to form an opening exposing a predetermined region of the semiconductor substrate. A conductive layer filling the opening is formed on the entire surface of the semiconductor substrate.

Abstract translation: 目的：提供一种使用氢倍半硅氧烷（HSQ）层作为层间电介质制造互连的方法，以简化形成互连的工艺，通过对HSQ层进行等离子体处理，使得HSQ层在 光刻工艺直接对HSQ层进行图案化。 构成：在半导体衬底（10）上形成低介电层。 对低介电层的整个表面进行等离子体处理。 将等离子体处理的低介电层图案化以形成暴露半导体衬底的预定区域的开口。 填充开口的导电层形成在半导体衬底的整个表面上。

公开(公告)号：KR1020000015110A

公开(公告)日：2000-03-15

申请号：KR1019980034851

申请日：1998-08-27

Applicant: 삼성전자주식회사

Inventor： 김재학

IPC: H01L21/28

Abstract: PURPOSE: A copper plug layer formation method of semiconductor devices provides enable to stable fill the copper into a contact hole of small size without voids by increasing the diameter of copper layer. CONSTITUTION: The method comprises the steps of interlayer insulator (3) having a contact hole (2) on the semiconductor substrate (1); forming a barrier layer and a copper seed (5) on the resultant structure; forming a first CVD copper layer (7) under kinetic controlled regime; forming a second CVD copper layer (7a) having a wide width compared to the first CVD copper layer by etching the first CVD copper layer (7) using the mixed gases of Cu(beta-diketonate) and alkene or alkyne gas under mass flow controlled regime; and forming a copper plug layer (9) without voids by filling copper into the contact hole.

Abstract translation: 目的：半导体器件的铜插塞层形成方法提供了通过增加铜层的直径来稳定地将铜填充到小尺寸的接触孔中而没有空隙。 构成：该方法包括在半导体衬底（1）上具有接触孔（2）的层间绝缘体（3）的步骤; 在所得结构上形成阻挡层和铜籽（5）; 在动力学控制方式下形成第一CVD铜层（7）; 通过使用Cu（β-二酮）和烯烃或炔烃的混合气体在质量流量控制下蚀刻第一CVD铜层（7），形成与第一CVD铜层相比宽的宽度的第二CVD铜层（7a） 政权; 以及通过将铜填充到所述接触孔中而形成无空隙的铜塞层（9）。

公开(公告)号：KR1019990034762A

公开(公告)日：1999-05-15

申请号：KR1019970056458

申请日：1997-10-30

Applicant: 삼성전자주식회사

Inventor： 김재학 ,  유봉녕 ,  최시영

IPC: H01L21/28

Abstract: 두께가 100Å보다 얇은 물질층을 다층 장벽층의 하나로 포함하는 반도체 장치의 제조공정에서 장벽층 형성방법을 개시한다. 상기 얇은 물질층은 상기 다층 장벽층이 전면에 형성되어 있는 콘택홀에 도전성 플러그 예컨데, 텅스텐 플러그를 채우는 과정에서 텅스텐 플러그의 소오스 가스에서 발생되는 불소와 상기 장벽층내의 반도체 기판과 반응하고 남은 티타늄과 반응하는 것을 억제한다. 이 결과, 상기 콘택홀에 도전성 플러그를 채우는 과정에서 장벽층의 저항이 증가되는 것을 방지할 수 있다. 더욱이, 상기 다층 장벽층을 형성한 이후, 그 결과물을 RTN처리함으로써 상기 도전성 플러그의 콘택저항은 더욱 안정된다.