公开(公告)号：AU2003298240A1

公开(公告)日：2004-06-23

申请号：AU2003298240

申请日：2003-11-14

Applicant: IBM

Inventor： CARGNONI ROBERT ALAN ,  GUTHRIE GUY LYNN ,  STARKE WILLIAM JOHN ,  ARIMILLI RAVI KUMAR

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F13/24

Abstract: A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.

公开(公告)号：CA2508044A1

公开(公告)日：2004-06-17

申请号：CA2508044

申请日：2003-11-14

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  CARGNONI ROBERT ALAN ,  STARKE WILLIAM JOHN ,  GUTHRIE GUY LYNN

IPC: G06F9/22 ,  G06F9/46 ,  G06F9/48 ,  G06F12/00

Abstract: A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor the memory, independent of the operating system running on the processor.

公开(公告)号：AT231257T

公开(公告)日：2003-02-15

申请号：AT95480127

申请日：1995-09-08

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  KAISER JOHN MICHAEL

IPC: G06F15/16 ,  G06F13/362 ,  G06F13/364 ,  G06F15/177

Abstract: A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus utilization via prioritization of all of the requested bus operations and pipelining appropriate bus grants. Intelligent bus request information is transferred to the system controller via encoding and serialization techniques.

公开(公告)号：DE69900797T2

公开(公告)日：2002-09-19

申请号：DE69900797

申请日：1999-02-15

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: A cache coherency protocol uses a "Tagged" coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars. The Tagged protocol can be combined with existing and new cache coherency protocols. The invention further contemplates independent optimization of cache operations using the Tagged state.

公开(公告)号：DE69900797D1

公开(公告)日：2002-03-14

申请号：DE69900797

申请日：1999-02-15

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08

Abstract: A cache coherency protocol uses a "Tagged" coherency state to track responsibility for writing a modified value back to system memory, allowing intervention of the value without immediately writing it back to system memory, thus increasing memory bandwidth. The Tagged state can migrate across the caches (horizontally) when assigned to a cache line that has most recently loaded the modified value. Historical states relating to the Tagged state may further be used. The invention may also be applied to a multi-processor computer system having clustered processing units, such that the Tagged state can be applied to one of the cache lines in each group of caches that support separate processing unit clusters. Priorities are assigned to different cache states, including the Tagged state, for responding to a request to access a corresponding memory block. Any tagged intervention response can be forwarded only to selected caches that could be affected by the intervention response, using cross-bars. The Tagged protocol can be combined with existing and new cache coherency protocols. The invention further contemplates independent optimization of cache operations using the Tagged state.

公开(公告)号：GB2325764B

公开(公告)日：2001-12-12

申请号：GB9806536

申请日：1998-03-27

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAMS DEREK EDWARD

IPC: G06F12/08 ,  G06F13/16

Abstract: Cache and architectural functions within a cache controller are layered and provided with generic interfaces. Layering cache and architectural operations allows the definition of generic interfaces between controller logic and bus interface units within the controller. The generic interfaces are defined by extracting the essence of supported operations into a generic protocol. The interfaces themselves may be pulsed or held interfaces, depending on the character of the operation. Because the controller logic is isolated from the specific protocols required by a processor or bus architecture, the design may be directly transferred to new controllers for different protocols or processors by modifying the bus interface units appropriately.

公开(公告)号：CZ360499A3

公开(公告)日：2000-07-12

申请号：CZ360499

申请日：1998-04-03

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  KAISER JOHN MICHAEL ,  LEWIS JERRY DON

IPC: G06F12/0806 ,  G06F12/08

公开(公告)号：SG68034A1

公开(公告)日：1999-10-19

申请号：SG1998000619

申请日：1998-03-25

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON

IPC: G06F12/08 ,  G06F9/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/42

公开(公告)号：GB2325763A

公开(公告)日：1998-12-02

申请号：GB9806476

申请日：1998-03-27

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAMS DEREK EDWARD

IPC: G06F12/08 ,  G06F13/16

Abstract: Cache and architectural-specific functions within a cache controller are layered (separated) to permit complex operations to be split into equivalent simple operations. Architectural variants of basic operations may thus be devolved, 310, into distinct cache and architectural operations and handled separately. The logic supporting the complex operations may thus be simplified and run faster. The functions are handled by respective controller units (212, 214, Fig 2).

公开(公告)号：GB2325541A

公开(公告)日：1998-11-25

申请号：GB9806453

申请日：1998-03-27

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DODSON JOHN STEVEN ,  LEWIS JERRY DON ,  WILLIAMS DEREK EDWARD

IPC: G06F12/08

Abstract: Cache (e.g read/write) and architectural specific (e.g data move, status change) functions are layered (separated) within a cache controller, simplifying design requirements. Faster performance may be achieved and individual segments of the overall design may be individually tested and formally verified. Transition between memory consistency models is also facilitated. Different segments of the overall design may be implemented in distinct integrated circuits, allowing less expensive processes to be employed where suitable. The cache and architectural functions are handled by respective controller units 212, 214.