公开(公告)号：CA2349569C

公开(公告)日：2005-04-05

申请号：CA2349569

申请日：1999-12-10

Applicant: IBM

Inventor： DEAN MARK EDWARD ,  ELMAN ANNA ,  BAUMGARTNER YOANNA

IPC: G06F12/00 ,  G06F12/08 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local inteconnect, and a node controller interposed between t he local interconnect and the node interconnect. In responce to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request to the remote processing node via the node interconnect. Thereafter, in response to receipt of a response to the read request from the remote processing node, the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processing scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

公开(公告)号：CA2280125C

公开(公告)日：2003-01-07

申请号：CA2280125

申请日：1999-08-12

Applicant: IBM

Inventor： GLASCO DAVID BRIAN ,  IACHETTA RICHARD NICHOLAS JR ,  CARPENTER GARY DALE ,  DEAN MARK EDWARD

IPC: G06F15/163 ,  G06F12/08 ,  G06F15/173

Abstract: The invention relates to memory access and provided non-uniform memory acces s (NUMA) data processing system includes a node interconnect to which at least a firs t processing node and a second processing node are coupled. The first and the second processing node s each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnec t and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the reques t transaction should be processed at the second processing node.

公开(公告)号：PL348253A1

公开(公告)日：2002-05-20

申请号：PL34825399

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F9/48 ,  G06F15/173 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：HU0104536A2

公开(公告)日：2002-03-28

申请号：HU0104536

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEAN MARK EDWARD ,  DEBACKER PHILIPPE LOUIS ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F9/48 ,  G06F15/173 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：CZ20012154A3

公开(公告)日：2001-09-12

申请号：CZ20012154

申请日：1999-11-30

Applicant: IBM

Inventor： CARPENTER GARY DALE ,  DEBACKER PHILIPPE LOUIS ,  DEAN MARK EDWARD ,  GLASCO DAVID BRIAN ,  ROCKHOLD RONALD LYNN

IPC: G06F15/173 ,  G06F9/48 ,  G06F9/46

Abstract: A non-uniform memory access (NUMA) computer system includes at least two nodes coupled by a node interconnect, where at least one of the nodes includes a processor for servicing interrupts. The nodes are partitioned into external interrupt domains so that an external interrupt is always presented to a processor within the external interrupt domain in which the interrupt occurs. Although each external interrupt domain typically includes only a single node, interrupt channeling or interrupt funneling may be implemented to route external interrupts across node boundaries for presentation to a processor. Once presented to a processor, interrupt handling software may then execute on any processor to service the external interrupt. Servicing external interrupts is expedited by reducing the size of the interrupt handler polling chain as compared to prior art methods. In addition to external interrupts, the interrupt architecture of the present invention supports inter-processor interrupts (IPIs) by which any processor may interrupt itself or one or more other processors in the NUMA computer system. IPIs are triggered by writing to memory mapped registers in global system memory, which facilitates the transmission of IPIs across node boundaries and permits multicast IPIs to be triggered simply by transmitting one write transaction to each node containing a processor to be interrupted. The interrupt hardware within each node is also distributed for scalability, with the hardware components communicating via interrupt transactions conveyed across shared communication paths.

公开(公告)号：CA2349569A1

公开(公告)日：2000-06-22

申请号：CA2349569

申请日：1999-12-10

Applicant: IBM

Inventor： BAUMGARTNER YOANNA ,  ELMAN ANNA ,  DEAN MARK EDWARD

IPC: G06F12/00 ,  G06F12/08 ,  G06F15/16

Abstract: A non-uniform memory access (NUMA) computer system includes at least a local processing node and a remote processing node that are each coupled to a node interconnect. The local processing node includes a local interconnect, a processor and a system memory coupled to the local inteconnect, and a node controller interposed between the local interconnect and the node interconnect. In responce to receipt of a read request from the local interconnect, the node controller speculatively transmits the read request t o the remote processing node via the node interconnect. Thereafter, in respons e to receipt of a response to the read request from the remote processing node , the node controller handles the response in accordance with a resolution of the read request at the local processing node. For example, in one processin g scenario, data contained in the response received from the remote processing node is discarded by the node controller if the read request received a Modified Intervention coherency response at the local processing node.

公开(公告)号：DE69030688T2

公开(公告)日：1997-11-13

申请号：DE69030688

申请日：1990-06-11

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F13/36 ,  G06F13/28 ,  G06F13/362 ,  G06F13/364

Abstract: A logic circuit external to a microprocessor monitors selected processor I/O pins to determine the current processor cycle and, in response to a hold request signal, drives the processor into a hold state at the appropriate time in the cycle. The logic circuit also includes a "lockbus" feature that, when the processor is not idle, "locks" the microprocessor to the local CPU bus for a predetermined period of time immediately after the processor is released from a hold state.

公开(公告)号：FI96244B

公开(公告)日：1996-02-15

申请号：FI891788

申请日：1989-04-14

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：FI95175C

公开(公告)日：1995-12-27

申请号：FI891787

申请日：1989-04-14

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F9/38 ,  G06F12/08

公开(公告)号：ES2078237T3

公开(公告)日：1995-12-16

申请号：ES89305307

申请日：1989-05-25

Applicant: IBM

Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

IPC: G06F12/08

Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.