公开(公告)号：FR2981472A1

公开(公告)日：2013-04-19

申请号：FR1202668

申请日：2012-10-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAMMEL BERNDT ,  GOTTFERT RAINER ,  OTTERSTEDT JAN

IPC: G06F11/10

Abstract: Procédé de reconstruction d'une FIP A, caractérisé en ce qu'on met à disposition une somme C de contrôle dans une mémoire morte, on produit une FIP B erronée et on reconstruit une FIP A à partir de B au moyen d'un algorithme de correction d'erreurs.

公开(公告)号：FR2978591A1

公开(公告)日：2013-02-01

申请号：FR1202102

申请日：2012-07-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NIRSCHL THOMAS ,  OTTERSTEDT JAN ,  SAVIGNAC DOMINIQUE ,  ALLERS WOLF

IPC: G11C7/12

Abstract: Mémoire (100) qui comprend une cellule (102) de mémoire, un élément (104) d'accumulation d'énergie configuré pour prendre en charge une programmation de la cellule (100) de mémoire, une alimentation (106) en énergie reliée à l'élément (104) d'accumulation d'énergie et une unité (108) de commande configurée pour activer l'alimentation (106) en énergie.

公开(公告)号：DE102005052293A1

公开(公告)日：2007-05-03

申请号：DE102005052293

申请日：2005-11-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEDLAK HOLGER ,  OTTERSTEDT JAN

IPC: G11C11/406 ,  G06F12/16

Abstract: The circuit (100) has a set of memory regions (120-0 - 120-N) whose sequence depends on assigned logical addresses. A control unit (130) provides a value and a preset value, when a user memory region exists and does not exist, respectively, during writing in a target memory region. The contents of a nearest memory region and the lowest memory region are newly written and the control values of the nearest and lowest regions are changed, when the nearest region exit and does not exist, respectively, when a preset condition is fulfilled and the user region exists. Independent claims are also included for the following: (1) a method for writing in a target memory region of a memory circuit (2) a program with a program code to execute a method of writing in a target memory region, when the program is executed in a processor.

公开(公告)号：DE50305595D1

公开(公告)日：2006-12-14

申请号：DE50305595

申请日：2003-07-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GAIL MARKUS ,  OTTERSTEDT JAN

IPC: G06F1/00 ,  G06F11/28 ,  G06F21/52 ,  G06F21/71

公开(公告)号：DE10161302B4

公开(公告)日：2006-11-16

申请号：DE10161302

申请日：2001-12-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OTTERSTEDT JAN ,  SCHMID GUENTER

IPC: G07C11/00 ,  G07C9/00

公开(公告)号：DE102004027372B4

公开(公告)日：2006-03-30

申请号：DE102004027372

申请日：2004-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： OTTERSTEDT JAN

IPC: H03K19/177 ,  G06F12/14 ,  G06F15/78 ,  G06F21/75 ,  H03K19/173 ,  H04L12/22

Abstract: A configurable logic circuit having a plurality of logic blocks and a connecting structure, via which the logic blocks are interconnectable, wherein the logic blocks are implemented in dual rail technique.