REDUCED COMPLEXITY SLIDING WINDOW BASED EQUALIZER

    公开(公告)号:CA2530518A1

    公开(公告)日:2005-01-13

    申请号:CA2530518

    申请日:2004-06-24

    Abstract: The present invention has many aspects. One aspect of the invention is to perform equalization using a sliding window approach. A second aspect reuses information derived for each window for use by a subsequent window. A third aspect utilizes a discrete Fourier transform based approach for the equalization. A fourth aspect relates to handling oversampling of the receiv ed signals and channel responses. A fifth aspect relates to handling multiple reception antennas. A sixth embodiment relates to handling both oversampling and multiple reception antennas.

    84.
    发明专利
    未知

    公开(公告)号:NO20042243L

    公开(公告)日:2004-05-28

    申请号:NO20042243

    申请日:2004-05-28

    Abstract: The number of users and data capacity of wireless systems are increased by employing apparatus and method for increasing the number of spreading codes available in the system by providing a mechanism to reuse the already allocated spreading code or use the codes that may correlate to those already being used within the same sector/cell. This, in return, provides capacity improvement proportional to the number of added base station (BS) antennas for each cell. An antenna null steering technique for code allocation maintains the cross correlation properties of the codes only for the desired user and to obtain a gain in capacity improvement.

    86.
    发明专利
    未知

    公开(公告)号:ES2144985T1

    公开(公告)日:2000-07-01

    申请号:ES98910290

    申请日:1998-03-11

    Abstract: A receiver for receiving a CDMA communication signal that is wirelessly transmitted includes a system for correcting phase errors in an information signal which has been transmitted. The correction system comprises circuitry for generating a mixing signal and for combining the mixing signal with said information signal to produce a correction signal. An analyzer analyzes the phase of said correction signal and generates an error signal based on the deviation of the analyzed phase from a reference phase. A bandwidth controller which recursively adjusts the phase of the correction signal such that the phase of said correction signal is substantially equal to said reference phase. The bandwidth controller then selects a bandwidth within an adjustable range based on the correction signal, estimates an offset by interrogating the error signal, and modifies said correction signal by the offset.

    88.
    发明专利
    未知

    公开(公告)号:DE60319373T2

    公开(公告)日:2009-02-19

    申请号:DE60319373

    申请日:2003-06-05

    Abstract: An analog/digital gain control device avoid some of the requirements associated with the nature of a closed-loop AGC circuits and which meets the remaining requirements without much difficulty uses an analog to digital conversion method that increases the number of effective ADC bits by compressing the baseband input analog signal using a logarithmic circuit. After the compressed analog signal is converted into a digital signal, a digital anti-log process or look-up table (LUT) is used to expand the digital signal back to the original linear scale. The word size of the output of the anti-log process is larger than the input word size due to the nature of the anti-log function. To reduce the word size of the digital signal an open loop normalization technique can be applied.

    METODO Y APARATO PARA LA CODIFICACION DEL INDICADOR DE CALIDAD DE CANAL Y BITS DE INFORMACION DE CONTROL PARA LA PRECODIFICACION

    公开(公告)号:AR063091A1

    公开(公告)日:2008-12-23

    申请号:ARP070104353

    申请日:2007-10-02

    Abstract: Se revela un método y aparato para la codificacion del indicador de calidad de canal (CQl) y los bits de informacion de control de precodificacion (PCI). Cada uno de los bits de entrada, como los bits de CQl y los bits de informacion de control de precodificacion, tiene una significacion particular. Los bits de entrada se codifican con una codificacion de bloque lineal. Los bits de entrada se proporciona con una proteccion de error desigual basada en la significacion de cada bit de entrada. Los bits de entrada pueden duplicarse basándose en el significado de cada bit de entrada y puede realizarse una codificacion de proteccion igual. Puede generarse una matriz generadora para la codificacion por operacion elemental de secuencias base convencionales para proporcionar más proteccion al bit más significativo (MSB).

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