公开(公告)号：WO1981000476A1

公开(公告)日：1981-02-19

申请号：PCT/US1980000939

申请日：1980-07-18

Applicant: NCR CORP

Inventor： NCR CORP ,  THOMAS J

IPC: G06K07/14

CPC classification number: G06K19/06037

Abstract: A machine readable code (10) in the form of a matrix array of dots arranged in rows and columns represents characters by respective columns of m dots. Each column contains a repeated n-bit pattern and is such that no block of n consecutive bit positions occurs in the column representing any other character, all the blocks of n consecutive bit positions within a given column being related by cyclic permutation. The code reader (16) Spans more than n bit positions but less than a full column.

Abstract translation: 以行和列排列的矩阵阵列阵列形式的机器可读代码（10）代表由m个点的相应列表示的字符。 每列包含重复的n位模式，并且使得在表示任何其他字符的列中不存在n个连续位位置的块，给定列中的n个连续位位置的所有块通过循环置换相关。 代码阅读器（16）跨越n位，但小于全列。

公开(公告)号：WO1980002760A1

公开(公告)日：1980-12-11

申请号：PCT/US1980000666

申请日：1980-05-29

Applicant: NCR CORP

Inventor： NCR CORP ,  AMACHER G ,  NASEEM S

IPC: G06K07/10

CPC classification number: G06K7/0166

Abstract: A symbol decoding system incorporated in a NMOS/LSI chip (24) generates asynchronously binary data in response to the scanning of bars and spaces of the symbol. The binary data may represent each bar or space as a numerical character, a margin or a center band of the symbol. The binary data also includes data identifying respective bars and spaces (MARK) and if the character generated is valid or invalid (EQUAL). The validity signal is generated by comparing a count derived from scanning four consecutive intervals with the count from scanning the previous four consecutive intervals. Logic circuits (52, 56, 60) generate a time delay period allowing the binary data to be generated asynchronously during the delay period. At the end of the delay period the binary data is outputted to a utilizing device (28) for selecting the valid data from the data outputted by the decoding system.

公开(公告)号：WO1980002202A1

公开(公告)日：1980-10-16

申请号：PCT/US1980000339

申请日：1980-03-31

Applicant: NCR CORP

Inventor： NCR CORP ,  MOHR S

IPC: G02B07/02

CPC classification number: G02B7/007 ,  Y10T403/7005

Abstract: A lens mounting for enabling rapid changes of lenses wherein a lens carrying structure (48) is arranged to be detachably secured to an apertured support structure (25, 30) by virtue of lugs (50) provided on the lens carrying structure (48) engaging between a planar, annular, spring element (32) and a rigid portion or portions (54) of the support structure (25, 30). Owing to the resilience of at least a portion (56) of the spring element (32), the latter biases the lugs (50) against said rigid portions (54), thereby securing the two structures together. In the preferred embodiment, the rigid portions (54) are inwardly extending lugs of a mounting plate (30) engaging with outwardly extending lugs (50) of the lens carrying structure (48). In another embodiment, the spring element (32) and mounting plate (30) are secured to the lens carrying structure (48) and the outwardly extending lugs are provided on the support structure (25).

Abstract translation: 一种透镜安装件，用于实现透镜的快速变换，其中透镜承载结构（48）被布置成通过设置在透镜承载结构（48）上的凸耳（50）可拆卸地固定到有孔支撑结构（25,30）上， 在平面的，环形的弹簧元件（32）和支撑结构（25,30）的刚性部分或部分（54）之间。 由于弹簧元件（32）的至少一部分（56）的弹性，后者将凸耳（50）偏压抵靠所述刚性部分（54），从而将两个结构固定在一起。 在优选实施例中，刚性部分（54）是与透镜承载结构（48）的向外延伸的凸耳（50）接合的安装板（30）的向内延伸的凸耳。 在另一个实施例中，弹簧元件（32）和安装板（30）固定到透镜承载结构（48），并且向外延伸的凸耳设置在支撑结构（25）上。

公开(公告)号：WO1980001965A1

公开(公告)日：1980-09-18

申请号：PCT/US1980000251

申请日：1980-03-10

Applicant: NCR CORP

Inventor： NCR CORP ,  LOCKWOOD G

IPC: G11C11/40

CPC classification number: G11C14/00

Abstract: A volatile/non-volatile RAM cell employing a bistable multivibrator with non-volatile, alterable-threshold capacitors (307, 308) coupled to the output terminals (A, B) thereof to provide backup data storage in a power-down situation The non-volatile capacitors each have a non-alterable section (307A, 308A) and an alterable section (307B, 308B), the non-alterable section having either a depletion or an enhancement threshold. The RAM cell incorporates both polysilicon resistors (305, 306) and enhancement mode devices (309, 310) in the load circuits of each cell to produce boot-strapping of the voltage on one of the multivibrator terminals (A, B) during a volatile/non-volatile write operation. A non-inverted restore of digital information to the bistable multivibrator is accomplished by simultaneous application of a step voltage to the cell power line (123A) and a restore pulse to the gate (307C, 308C) of the non-volatile capacitors. An alternative inverted restore for a cell utilizing depletion thresholds in the non-alterable sections (307A, 308A) of the non-volatile capacitors, (307, 308) involves grounding the gate electrode (307C, 308C) of the non-volatile capacitors to restore the previously written information to the multivibrator. A data processing system employing the volatile/non-volatile RAM system with a single five volt power supply (40) and a write/restore/erase signal generator (50), all implemented in five volt, n-channel silicon-insulator-silicon (SIS) device technology, is shown.

Abstract translation: 使用具有耦合到其输出端子（A，B）的非易失性，可变阈值电容器（307,308）的双稳态多谐振荡器的易失性/非易失性RAM单元以在掉电情况下提供备份数据存储非 - 每个易失性电容器具有不可改变的部分（307A，308A）和可变形部分（307B，308B），所述不可更改部分具有耗尽或增强阈值。 RAM单元在每个单元的负载电路中并入多晶硅电阻器（305,306）和增强模式器件（309,310），以在易失性存储器中产生在多谐振荡器端子（A，B）之一上的电压的引导带 /非易失性写操作。 通过向单元电力线（123A）同步施加阶梯电压和向非易失性电容器的栅极（307C，308C）施加恢复脉冲来实现数字信息到双稳态多谐振荡器的非反相恢复。 在非易失性电容器（307,308）的不可改变部分（307A，308A）中使用耗尽阈值的单元的替代反向恢复涉及使非易失性电容器的栅电极（307C，308C）接地到 将先前写入的信息恢复到多谐振荡器。 一种使用具有单个五伏电源（40）的易失性/非易失性RAM系统和写入/恢复/擦除信号发生器（50）的数据处理系统，全部在五伏的n沟道硅绝缘体硅 （SIS）设备技术。

公开(公告)号：WO1980001521A1

公开(公告)日：1980-07-24

申请号：PCT/US1980000024

申请日：1980-01-11

Applicant: NCR CORP

Inventor： NCR CORP ,  QUACK S ,  MOORE H

IPC: G06F15/16

CPC classification number: G06F13/18

Abstract: A data processing system includes first and second data processors (20, 38) and first and second memories (26, 42), the first processor (20) being adapted to write data into the first memory (26) and the second processor being adapted to write data into the first and second memories (26, 42). The first processor (20) which is slower than the second processor (38), has priority of access to the first memory (26). When the second processor (38) is unable to write into the first memory (26) because of a conflict with the first processor (20), the data stored in the second memory (42) by the second processor (38) is transferred to the first memory (26) after completion of the access operation by the first processor (20). Also, data stored by the first processor (20) in the first memory (26) is transferred to the second memory (42) under the control of the second processor (38). Thus both processors (20, 38) will have access to the same data.

公开(公告)号：WO1980001425A1

公开(公告)日：1980-07-10

申请号：PCT/US1979001141

申请日：1979-12-28

Applicant: NCR CORP

Inventor： NCR CORP ,  PATEL N

IPC: G11C07/00

CPC classification number: G11C11/4072 ,  G11C11/406

Abstract: A circuit which efficiently controls the refresh operation of a dynamic memory. The refresh control circuit operates such that a dynamic memory (28) coupled to a processing means responds to a memory access signal (BMREQ) for a read/write operation and a first refresh control signal (BMREF) for a memory refresh operation. First circuits (30, 32) provide a second periodic refresh control signal (REFREQ), and second circuits (34, 40) refresh the memory under the control of either of the first (BMREF) or second (REFREQ) refresh control signals. A third circuit (20) responsive to the memory access signal (BMREQ) and the second refresh control signal (REFREQ) awards priority of access to the memory (28) in accordance with the first active signal which it receives. A fourth circuit (20) puts the processing means in a hold condition when priority is awarded to the second refresh control signal (REFREQ). In a power down condition a (BRST) signal enables gates (42) having a battery back up to permit the dynamic memory to be refreshed.

Abstract translation: 一种有效地控制动态存储器的刷新操作的电路。 刷新控制电路的操作使得耦合到处理装置的动态存储器（28）响应用于读/写操作的存储器访问信号（BMREQ）和用于存储器刷新操作的第一刷新控制信号（BMREF）。 第一电路（30,32）提供第二周期性刷新控制信号（REFREQ），第二电路（34,40）在第一（BMREF）或第二（REFREQ）刷新控制信号中的任一个的控制下刷新存储器。 响应于存储器访问信号（BMREQ）和第二刷新控制信号（REFREQ）的第三电路（20）根据接收到的第一有效信号来授予对存储器（28）的访问的优先级。 当优先权被授予第二刷新控制信号（REFREQ）时，第四电路（20）将处理装置置于保持状态。 在断电状态下，（BRST）信号使得具有电池备份的门（42）能够刷新动态存储器。

公开(公告)号：WO1980000633A1

公开(公告)日：1980-04-03

申请号：PCT/US1979000660

申请日：1979-08-23

Applicant: NCR CORP

Inventor： NCR CORP ,  WARD W

IPC: G11C19/28

CPC classification number: G11C19/36 ,  G11C19/285

Abstract: A data storage system (10) for storing multilevel, non-binary data includes a charge coupled device shift register (12) and a detection circuit (20) for detecting the data level represented by the charge or signal within each cell location of the shift register (12). The detection circuit (20) includes a sense amplifier (30) for comparing the signals from two adjacent cell locations (b0, b1), with one signal representing a known data level. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors (50, 52) cause the output of an incrementing digital-to-analog converter (40) to be added to one of the signals prior to comparison. The output of the sense amplifier (30) is provided to a flip-flop (32), which controls the switching transistors (50, 52). The outputs of the sense amplifier (30) and flip-flop (32) are connected to an EXCLUSIVE NOR gate (54), whose output enables an up/down counter (56), which in turn provides a detected data level.

公开(公告)号：WO1980000387A1

公开(公告)日：1980-03-06

申请号：PCT/US1979000565

申请日：1979-07-31

Applicant: NCR CORP

Inventor： NCR CORP ,  WARD W

IPC: G11C19/28

CPC classification number: G11C19/285

Abstract: A data storage system (10) includes a charge coupled device shift register (12) and a detection circuit (20) for detecting the binary value represented by the charge level or signal within each cell location of the shift register. The detection circuit (20) includes a sense amplifier (30) for comparing the signals from two adjacent cell locations (b0, b1), with one signal representing a known binary value. The comparison of adjacent cell locations compensates for signal losses during shifting, since the losses experienced by adjacent cell locations are nearly identical. Switching transistors (40, 42) cause an adjustment voltage (Va) to be added to one of the signals prior to comparison. The output of the sense amplifier is provided to a flip-flop (32), which controls the switching transistors and is set to a predetermined state whenever a reference data item is located in the cell location (b0) providing the signal representing the known binary value.

公开(公告)号：WO1979000912A1

公开(公告)日：1979-11-15

申请号：PCT/US1978000084

申请日：1978-09-19

Applicant: NCR CORP

Inventor： NCR CORP ,  LAUFFER D ,  WARD W

IPC: G11C11/40

CPC classification number: G06F13/4243 ,  G11C5/00 ,  G11C5/066

Abstract: A circuit for reducing the number of external pins or terminals on a memory device includes a counter circuit which periodically causes the signal on a first external pin to be provided to the power terminal of an internal power supply within the memory device and, at the same time, causes the ground level signal on a second external pin to be provided to the ground terminal of the internal power supply. At other times during the receipt of signals on the two external pins, the signal on the first pin provides both memory select and clocking functions and the signal on the second pin provides memory mode select, address, and data input and output functions.

Abstract translation: 用于减少存储器件上的外部引脚或端子数量的电路包括周期性地使第一外部引脚上的信号提供给存储器件内部电源的电源端的计数器电路，并且在相同 时间，将第二外部引脚上的接地电平信号提供给内部电源的接地端子。 在接收两个外部引脚上的信号的其他时间，第一个引脚上的信号提供存储器选择和时钟功能，第二个引脚上的信号提供存储模式选择，地址和数据输入和输出功能。

公开(公告)号：WO1982004162A1

公开(公告)日：1982-11-25

申请号：PCT/US1982000600

申请日：1982-05-07

Applicant: NCR CORP

Inventor： NCR CORP ,  TOPICH JAMES ANTHONY

IPC: H01L29/78

CPC classification number: H01L29/792

Abstract: An alterable threshold memory device (100) includes a semiconductor substrate (11), a memory silicon oxide layer (12) having a thickness lying in the range of 25-40 Angstroms, a silicon nitride layer (13), an interfacial silicon oxide layer (14) having a thickness lying in the range of 30-60 Angstroms, and a polysilicon gate electrode. The device (100) has a high write speed and a large memory window. The nitride layer (13) may have a thickness lying in the range 150-250 Angstroms, enabling the utilization of low write voltages.

Abstract translation: 可变阈值存储器件（100）包括半导体衬底（11），具有在25-40埃范围内的厚度的存储氧化硅层（12），氮化硅层（13），界面氧化硅层 （14），其厚度在30-60埃的范围内，以及多晶硅栅电极。 设备（100）具有高写入速度和大的存储器窗口。 氮化物层（13）可以具有在150-250埃范围内的厚度，从而能够利用低写入电压。