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    85.
    发明专利
    未知

    公开(公告)号：FR2801678B1

    公开(公告)日：2002-02-01

    申请号：FR9915113

    申请日：1999-11-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD

    IPC: G01R19/165 ,  G05F3/24 ,  G11C5/14 ,  G11C7/00

    Abstract: A device for detecting the application of a high voltage signal to an internal node of an integrated circuit includes a high-voltage divider circuit and a threshold detection circuit. The threshold detection circuit receives a signal given by the output of the divider circuit, and provides a threshold crossing detection signal at an output thereof based upon the signal crossing a threshold. The detection circuit is connected between the logic supply voltage and ground, and further includes a negative feedback loop. The negative feedback loop is connected to the output of the divider circuit to limit the voltage build-up of the high voltage signal at the output thereof after the crossing of the detection threshold by the signal.

    86.
    发明专利
    未知

    公开(公告)号：FR2811164A1

    公开(公告)日：2002-01-04

    申请号：FR0008546

    申请日：2000-06-30

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD

    IPC: H02H7/20 ,  G09C1/00 ,  H03K17/10 ,  H03K17/693 ,  H04L9/10 ,  H03K17/26 ,  H03K17/56

    Abstract: The integrated circuit (1) with supply voltages including a reference voltage as the ground (Gnd), a logic voltage (Vdd) and a higher voltage (HV) comprises a protection device (2) associated with at least one element with the gate oxide for applying to a supply node (N) either the logic voltage in the conditions of normal functioning of integrated circuit, or the higher voltage in the conditions of abnormal functioning for breaking down the gate oxide to make the integrated circuit irreversibly unusable. The integrated circuit comprises means (4) for the detection of abnormal conditions for activating an alarm signal (IN) which is applied to the control input of the protection device (2). The protection device contains two switches functioning in complementary manner for applying the higher voltage or the logic voltage to the supply node (N), and a voltage translator with at least one cascade stage providing signals for the control of switches. The voltage translator contains in eahc of two branches a transistor connected to the higher voltage, a transistor connected to the ground, and at least one cascade transistor connected between the two transistors. The supply node (N) is for the application of logic voltage, and the higher voltage is applied to an external pin, or the higher voltage is delivered internally on the basis of logic voltage. The method for the protection of integrated circuit against abnormal uses includes an application of higher voltage instead of logic voltage to at least one logic element of integrated circuit.

    Memory cell of read-only type associated and implemented with dynamic random access memory (DRAM) cell, for use in computing technology
    87.
    发明专利
    Memory cell of read-only type associated and implemented with dynamic random access memory (DRAM) cell, for use in computing technology 未知

    公开(公告)号：FR2810452A1

    公开(公告)日：2001-12-21

    申请号：FR0007874

    申请日：2000-06-20

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  MALLARDEAU CATHERINE

    IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  G11C16/02

    Abstract: The memory cell structure of read-only type (20) with a double gate comprises the source (S), the drain (D), the floating gate (GF) and the control gate (GC), where the floating gate is formed by a standard gate (30) coupled to the first conducting electrode (31), which is similar to the first electrode (3) of the capacitor of DRAM cell (1), and the control electrode formed by the second conducting electrode (33) separated from the first electrode by an insulating layer (32), which is similar to the second electrode (5) of the capacitor separated from the first plate by an insulating layer (4). The manufacturing method includes a simultaneous formation of the double-gate structure of read-only type such as EPROM, EEPROM, or Flash-EEPROM, and the standard gate structure of type DRAM. The first electrode is formed of rough polycrystalline silicon. The manufacturing method comprises the steps: (a) The formation of the drain (D), the source (S), and the gate (G, 30) for each of the two cells. (b) The formation of the first electrode (3) as the first plate of capacitor, and simultaneously the electrode (31) of the double-gate cell. (c) The deposition of an insulating layer (4), and simultaneously of an insulating layer (32). (d) The formation of the second electrode (5) as the second plate of capacitor, and simultaneously of the electrode (33), which is the control gate (CG) of the double-gate cell. The insulating layer (32) is of a greater thickness than the insulating layer (4). The step (d) comprises two phases, the deposition of electrode (5) and the deposition of electrode (33), for the optimization of characteristics of the two cells. An integrated circuit is also claimed which comprises the double-gate cell, or the associated cell s.

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