公开(公告)号：WO2011153177A3

公开(公告)日：2012-03-01

申请号：PCT/US2011038654

申请日：2011-05-31

Applicant: ALTERA CORP

Inventor： FUNG RYAN

IPC: G11C7/10 ,  G11C7/22 ,  H03K19/173

CPC classification number: G11C7/222 ,  G11C7/1036 ,  G11C7/1078 ,  G11C7/1093

Abstract: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

Abstract translation: 一种装置包括耦合到电子装置的接口电路。 接口电路使用选通信号提供与电子设备的源同步通信。 接口电路被配置为对选通信号进行门控，以便与电子设备成功通信。

公开(公告)号：WO2011153177A2

公开(公告)日：2011-12-08

申请号：PCT/US2011/038654

申请日：2011-05-31

Applicant: ALTERA CORPORATION

Inventor： FUNG, Ryan

IPC: G11C7/10 ,  G11C7/22 ,  H03K19/173

CPC classification number: G11C7/222 ,  G11C7/1036 ,  G11C7/1078 ,  G11C7/1093

Abstract: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

Abstract translation: 一种装置包括耦合到电子装置的接口电路。 接口电路使用选通信号提供与电子设备的源同步通信。 接口电路被配置为对选通信号进行门控，以便与电子设备成功通信。

公开(公告)号：WO2006051455A1

公开(公告)日：2006-05-18

申请号：PCT/IB2005/053604

申请日：2005-11-04

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  VAN ACHT, Victor, M., G. ,  MARSMAN, Albert, W. ,  CHONG, Boon, K. ,  LAMBERT, Nicolaas ,  WOERLEE, Pierre, H. ,  IKKINK, Teunis, J.

Inventor： VAN ACHT, Victor, M., G. ,  MARSMAN, Albert, W. ,  CHONG, Boon, K. ,  LAMBERT, Nicolaas ,  WOERLEE, Pierre, H. ,  IKKINK, Teunis, J.

IPC: G11C7/10

CPC classification number: G11C7/1051 ,  G11C7/1036 ,  G11C7/1063 ,  G11C11/56

Abstract: A memory integrated circuit contains a sensing circuit (12) that receives signals from addressed memory cells. The sensing circuit determines in which of a number of ranges the signals fall, the number of ranges being greater than the number values to which the cells can be programmed. An output circuit is provided that is arranged to supply either only data words that have been inferred from the detection, or also further information that provides more information about the ranges that have been detected than the data words only. Dependent on a control signal from external terminals of the memory integrated circuit the output circuit supplies the data words only to the external terminals or also the further information about the detected ranges in addition to the data words.

Abstract translation: 存储器集成电路包含从寻址的存储器单元接收信号的感测电路（12）。 感测电路确定信号下降的范围中的哪一个，范围的数量大于可以编程单元的数字值。 提供了一种输出电路，其被布置为仅提供从检测中推断出的数据字，或者还提供了与仅数据字相比已经被检测的范围的更多信息的其他信息。 取决于来自存储器集成电路的外部端子的控制信号，输出电路仅将数据字提供给外部端子，或者除了数据字之外还提供关于检测范围的进一步信息。

公开(公告)号：WO03025939A2

公开(公告)日：2003-03-27

申请号：PCT/US0229527

申请日：2002-09-17

Applicant: SANDISK CORP ,  CERNEA RAUL ADRIAN

Inventor： CERNEA RAUL ADRIAN

IPC: G11C16/02 ,  G11C7/10 ,  G11C16/06

CPC classification number: G11C7/1048 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. The memory cells may be multistate memory cells. There is a shift register chain, having a stage for columns of the array. A strobe pulse is shifted through this shift register. The strobe points, with each clock, at and enables a different selecting circuit in sequence. That particular selecting circuit that has been enabled by the strobe will then perform a certain function. In a read mode, the selected selecting circuit will send the stored information through to the output buffer for output from the integrated circuit. And while in a programming mode, the selected selecting circuit will receive data from an input buffer. This data will be written into a memory cell.

Abstract translation: 选择存储器单元阵列的电路用于保持存储单元的读取数据或写入数据。 存储单元可以是多状态存储器单元。 有一个移位寄存器链，具有数组列的阶段。 选通脉冲通过该移位寄存器移位。 每个时钟的选通点依次处于并使能不同的选择电路。 那个已经被选通使能的特定选择电路然后将执行一定的功能。 在读取模式下，所选择的选择电路将存储的信息发送到输出缓冲器，以从集成电路输出。 而在编程模式下，所选择的选择电路将从输入缓冲器接收数据。 该数据将被写入存储单元。

公开(公告)号：WO2016144951A1

公开(公告)日：2016-09-15

申请号：PCT/US2016/021359

申请日：2016-03-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TIWARI, Sanjay

IPC: G11C7/06 ,  G11C7/22

CPC classification number: G11C7/1036 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

Abstract translation: 本公开的示例提供了用于在存储器中执行移位操作的装置和方法。 一个示例性方法包括执行移位操作，该第一元素存储在耦合到第一存取线的第一组存储器单元和存储器阵列的多条感测线以及存储在耦合到第一存储器单元的第二组存储器单元中的第二元件 第二访问线和存储器阵列的感测线的数量。 该方法可以包括通过执行不经由输入/输出（I / O）传送数据而执行的多个AND运算，OR运算，SHIFT运算和INVERT运算，来移动第一元素移动由第二元素限定的位数位置。 线。

公开(公告)号：WO2016112151A1

公开(公告)日：2016-07-14

申请号：PCT/US2016/012415

申请日：2016-01-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WHEELER, Kyle B. ,  MURPHY, Richard C. ,  MANNING, Troy A. ,  KLEIN, Dean A.

IPC: G06F12/02 ,  G06F9/30 ,  G11C7/06

CPC classification number: G06F9/3877 ,  G06F15/7821 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4087 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

Abstract translation: 本公开的示例提供与生成和执行控制流有关的装置和方法。 示例性设备可以包括被配置为生成控制流指令的第一设备，以及包括存储器单元阵列的第二设备，执行控制流指令的执行单元，以及控制器，其被配置为控制控制流指令的执行 数据存储在数组中。

公开(公告)号：WO2013165774A1

公开(公告)日：2013-11-07

申请号：PCT/US2013/037958

申请日：2013-04-24

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： LIU, Bo ,  TSAI, Frank Wanfang ,  PARK, Jongmin ,  LI, Yan

IPC: G11C29/00 ,  G11C7/10 ,  G11C8/04

CPC classification number: G11C29/848 ,  G11C7/1036 ,  G11C8/04 ,  G11C29/78

Abstract: In a non-volatile memory circuit, techniques are presented so that bad columns can be ignored and/or replaced during memory data input and output operations. A column redundant circuit for this purpose reduces circuit size and improves performance. User data is grouped in an interleaved manner so that data belonging to consecutive logical address will be distributed into different physical locations. For example, all column data can be physically grouped into, say, 5 divisions and user data can be written into or accessed from one division after another consecutively. Each division has its own clock control. The column redundancy block can generate bad column locations' information and send it to control logic to switch the user clock to a different division clock, thereby skipping bad columns. By controlling the clocks for different columns, the user can directly access good columns without touching bad columns.

Abstract translation: 在非易失性存储器电路中，呈现技术，使得在存储器数据输入和输出操作期间可以忽略和/或替换坏列。 用于此目的的列冗余电路可减少电路尺寸并提高性能。 用户数据以交错方式分组，使得属于连续逻辑地址的数据将被分配到不同的物理位置。 例如，所有列数据可以被物理地分组到例如5个分区中，并且用户数据可以被连续地从一个分区写入或访问。 每个部门都有自己的时钟控制。 列冗余块可以产生错误的列位置信息，并将其发送到控制逻辑以将用户时钟切换到不同的分频时钟，从而跳过不良列。 通过控制不同列的时钟，用户可以直接访问好的列，而不会碰坏列。

公开(公告)号：WO2013062559A1

公开(公告)日：2013-05-02

申请号：PCT/US2011/058177

申请日：2011-10-27

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. ,  PICKETT, Matthew D. ,  WILLIAMS, R. Stanley ,  RIBEIRO, Gilberto M.

Inventor： PICKETT, Matthew D. ,  WILLIAMS, R. Stanley ,  RIBEIRO, Gilberto M.

IPC: G11C19/00 ,  G11C7/10

CPC classification number: G06F5/08 ,  G11C7/1012 ,  G11C7/1036 ,  G11C19/00 ,  G11C19/28 ,  G11C21/00

Abstract: Shiftable memory employs ring registers to shift a contiguous subset of data words stored in the ring registers within the shiftable memory. A shiftable memory includes a memory having built-in word-level shifting capability. The memory includes a plurality of ring registers to store data words. A contiguous subset of data words is shiftable between sets of the ring registers of the plurality from a first location to a second location within the memory. The contiguous subset of data words has a size that is smaller than a total size of the memory. The memory shifts only data words stored inside the contiguous subset when the contiguous subset is shifted.

Abstract translation: 可移动存储器使用振铃寄存器来移位存储在可移位存储器内的环形寄存器中的数据字的连续子集。 可移位存储器包括具有内置字级移位能力的存储器。 存储器包括多个用于存储数据字的环形寄存器。 数据字的连续子集可在存储器内的第一位置到第二位置的多个环形寄存器的集合之间移位。 数据字的连续子集具有小于存储器总大小的大小。 当连续子集移位时，存储器仅移动存储在连续子集内的数据字。

公开(公告)号：WO2013015960A3

公开(公告)日：2013-03-21

申请号：PCT/US2012045510

申请日：2012-07-05

Applicant: MICRON TECHNOLOGY INC ,  HENDRICKSON NICHOLAS

Inventor： HENDRICKSON NICHOLAS

IPC: G11C16/34

CPC classification number: G11C16/26 ,  G11C7/1033 ,  G11C7/1036 ,  G11C7/1039 ,  G11C7/106 ,  G11C11/5642 ,  G11C16/0458 ,  G11C16/0483 ,  G11C2207/2272 ,  G11C2211/5642

Abstract: Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory cells. In at least one method, a data state of a memory cell is determined during a first sense phase and is transferred while the memory cell experiences additional sense phases to determine additional portions of the data state of the memory cell.

Abstract translation: 公开了操作存储器件的装置和方法。 在一种这样的方法中，存储器单元的数据状态的第一部分被确定并从存储器件传送，同时继续确定相同存储器单元的数据状态的剩余部分。 在至少一种方法中，在第一感测阶段期间确定存储器单元的数据状态，并且在存储器单元经历额外的检测相位时传送，以确定存储器单元的数据状态的附加部分。

公开(公告)号：WO2011005427A1

公开(公告)日：2011-01-13

申请号：PCT/US2010/038616

申请日：2010-06-15

Applicant: SANDISK CORPORATION ,  CHIBVONGODZE, Hardwell ,  SAKAI, Manabu ,  KAMEI, Teruhiko

Inventor： CHIBVONGODZE, Hardwell ,  SAKAI, Manabu ,  KAMEI, Teruhiko

IPC: G11C7/10 ,  G11C11/56

CPC classification number: G11C11/5642 ,  G11C7/103 ,  G11C7/1036 ,  G11C19/00

Abstract: Selecting circuits for columns of an array of memory cells are used to hold read data or write data of the memory cells. In a first set of embodiments, a shift register chain, having a stage for columns of the array, has the columns arranged in a loop. For example, every other column or column group could be assessed as the pointer moves in first direction across the array, with the other half of the columns being accessed as the pointer moves back in the other direction. Another set of embodiments divides the columns into two groups and uses a pair of interleaved pointers, one for each set of columns, clocked at half speed. To control the access of the two sets, each of which is connected to a corresponding intermediate data bus. The intermediate data buses are then attached to a combined data bus, clocked at full speed.

Abstract translation: 选择存储器单元阵列的电路用于保持存储单元的读取数据或写入数据。 在第一组实施例中，具有阵列列的移位寄存器链具有以循环布置的列。 例如，当指针沿着阵列的第一方向移动时，可以评估每隔一列或列组，随着指针在另一个方向上向后移动，另外一半的列被访问。 另一组实施例将列分成两组，并且使用一对交错指针，每半组一列，以半速计时。 为了控制两个组的访问，每个集合都连接到相应的中间数据总线。 然后将中间数据总线连接到以全速计时的组合数据总线。