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    METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT
    81.
    发明申请
    METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权
    制造三维集成电路的方法

    公开(公告)号：US20140284849A1

    公开(公告)日：2014-09-25

    申请号：US14296419

    申请日：2014-06-04

    Applicant: Innetech (Tianjin) Electronics Co., Ltd.

    Inventor： Dongsheng LIU ,  Meng WANG

    IPC: H01L21/768 ,  C23C18/18 ,  C23C18/16 ,  B29C45/00

    CPC classification number: H01L21/768 ,  B29C45/0053 ,  B29C2045/0079 ,  C23C18/1608 ,  C23C18/1612 ,  C23C18/1641 ,  C23C18/1651 ,  C23C18/166 ,  C23C18/1868 ,  C23C18/204 ,  C23C18/208 ,  C23C18/32 ,  C23C18/36 ,  C23C18/38 ,  C23C18/405 ,  H05K3/185 ,  H05K2201/0129 ,  H05K2201/0236 ,  H05K2201/09118 ,  H05K2203/107

    Abstract: A method for manufacturing a three-dimensional integrated circuit. The method includes: 1) adding a non-metallic light-induced catalyst including an alcohol and/or an aldehyde to a thermoplastic carrier material, and molding the resulting mixture by an injection molding machine to form a structural component; 2) irradiating a surface of the structural component with a laser ray to form a line pattern thereon; 3) immersing the structural component in a metal ion solution at room temperature for between 5 and 7 minutes; 4) washing the structural component with distilled water, and immersing the structural component in an aqueous solution including a reducing agent for between 5 and 7 minutes to allow the surface of the structural component to form a metal core; and 5) performing electroless copper plating and medium-phosphorus electroless nickel plating on an area comprising the metal core to yield a conductor track.

    Abstract translation: 一种三维集成电路的制造方法。 该方法包括：1）向热塑性载体材料中加入包含醇和/或醛的非金属光诱导催化剂，并通过注塑机成型所得混合物以形成结构组分; 2）用激光照射结构部件的表面以在其上形成线图案; 3）在室温下将结构成分浸入金属离子溶液中5〜7分钟; 4）用蒸馏水洗涤结构组分，并将结构组分浸入包括还原剂的水溶液中5至7分钟以使结构组分的表面形成金属芯; 以及5）在包括所述金属芯的区域上执行无电镀铜和中磷化学镀镍以产生导体轨道。

    Embedded wiring board and a manufacturing method thereof
    82.
    发明授权
    Embedded wiring board and a manufacturing method thereof 有权
    嵌入式布线板及其制造方法

    公开(公告)号：US08217278B2

    公开(公告)日：2012-07-10

    申请号：US12613072

    申请日：2009-11-05

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K1/11

    CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

    Abstract: An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.

    Abstract translation: 嵌入布线板包括上布线层，下布线层，绝缘层，第一导电柱和第二导电柱。 上布线层包含上焊盘，下布线层包含下焊盘，绝缘层包含与上表面相对的上表面和下表面。 上垫片嵌入在上表面中，下垫片嵌入下表面。 第一导电柱位于绝缘层中，并且包括由上表面暴露的端面。 第一导电柱相对于上表面的高度大于上垫相对于上表面的深度。 此外，第二导电柱位于绝缘层中并连接在第一导电柱和下垫之间。

    Composite circuit substrate structure
    87.
    发明授权
    Composite circuit substrate structure 有权
    复合电路基板结构

    公开(公告)号：US07906200B2

    公开(公告)日：2011-03-15

    申请号：US12424057

    申请日：2009-04-15

    Applicant: Tzyy-Jang Tseng ,  Chih-Peng Fan

    Inventor： Tzyy-Jang Tseng ,  Chih-Peng Fan

    IPC: B32B9/00

    CPC classification number: H05K3/045 ,  H05K1/036 ,  H05K1/0366 ,  H05K3/107 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2201/029 ,  H05K2203/0723 ,  H05K2203/107 ,  Y10T428/24917 ,  Y10T428/24926

    Abstract: A composite circuit substrate structure includes a first dielectric layer, a second dielectric layer, a glass fiber structure, and a patterned circuit. The first dielectric layer has a first surface and a second surface opposite to each other. The second dielectric layer is disposed on the first dielectric layer and entirely connected to the first surface. The glass fiber structure is distributed in the second dielectric layer. The patterned circuit is embedded in the first dielectric layer from the second surface, and the patterned circuit is not contacted with the glass fiber structure.

    Abstract translation: 复合电路基板结构包括第一电介质层，第二电介质层，玻璃纤维结构和图案化电路。 第一介电层具有彼此相对的第一表面和第二表面。 第二电介质层设置在第一电介质层上并且完全连接到第一表面。 玻璃纤维结构分布在第二电介质层中。 图案化电路从第二表面嵌入第一电介质层中，并且图案化电路不与玻璃纤维结构接触。

    METAL-CLAD SUBSTRATE, AND METHOD FOR PRODUCTION THEREOF
    89.
    发明申请
    METAL-CLAD SUBSTRATE, AND METHOD FOR PRODUCTION THEREOF 审中-公开
    金属剥离基材及其生产方法

    公开(公告)号：US20100273014A1

    公开(公告)日：2010-10-28

    申请号：US12810762

    申请日：2008-12-24

    Applicant: Shiki Ueki

    Inventor： Shiki Ueki

    IPC: B32B15/08 ,  B05D5/12

    CPC classification number: H05K3/181 ,  H05K1/0373 ,  H05K2201/0236 ,  Y10T428/31678

    Abstract: A method for producing a metal-clad substrate, the method including: (a) forming, on a substrate, a resin layer containing a plating catalyst or a precursor thereof, which resin layer satisfies the following requirement 1; and (b) performing plating on the resin layer, Requirement 1: the resin layer contains the plating catalyst or a precursor thereof within a portion extending from a surface to a depth of 25 nm of the resin layer, in an amount in the range of 3×10−20 mol/nm3 to 30×10−20 mol/nm3 in terms of a content of a metal element thereof.

    Abstract translation: 一种金属包覆基板的制造方法，其特征在于，包括：（a）在基板上形成含有电镀催化剂或其前体的树脂层，所述树脂层满足以下要求1; （b）在树脂层上进行电镀，要素1：树脂层在从树脂层的表面延伸到深度25nm的部分内含有电镀催化剂或其前体，其量在 3×10-20mol / nm 3〜30×10〜20mol / nm 3。

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