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    METHOD FOR PRODUCING RIGID-FLEX CIRCUIT BOARD, AND RIGID-FLEX CIRCUIT BOARD
    81.
    发明公开
    METHOD FOR PRODUCING RIGID-FLEX CIRCUIT BOARD, AND RIGID-FLEX CIRCUIT BOARD 审中-公开
    VERFAHREN ZUR HERSTELLUNG EINER STARR-FLEXIBLEN PLATINE UND STARR-FLEXBLE PLATINE

    公开(公告)号：EP2262352A1

    公开(公告)日：2010-12-15

    申请号：EP09725063.3

    申请日：2009-03-12

    Applicant: Sumitomo Bakelite Co., Ltd.

    Inventor： YAMATO, Hajime

    IPC: H05K3/46 ,  H05K3/28

    CPC classification number: H05K3/4635 ,  H05K3/281 ,  H05K3/4611 ,  H05K3/4691 ,  H05K2201/09109 ,  Y10T29/49126

    Abstract: A method of manufacturing a rigid-flex circuit board includes preparing a first and a second coverlay film (200, 250), and a first and a second circuit substrate (100, 150) having a first and a second circuit (103, 153) formed thereon, and a first interlayer adhesive sheet (300); Stacking the first coverlay film (200), the first circuit substrate (100) disposed such that the first circuit (103) opposes the first coverlay film (200), the first interlayer adhesive sheet (300) located in a region where a rigid portion (700) is to be formed, the second coverlay film (250), and the second circuit substrate (150) disposed such that the second circuit (153) opposes the second coverlay film (250), and executing a heat-pressing process.

    Abstract translation: 一种刚性柔性电路板的制造方法包括制备第一和第二覆盖膜（200,250）以及具有第一和第二电路（103,153）的第一和第二电路基板（100,150） 和第一层间粘合片（300）; 堆叠第一覆盖膜（200），第一电路基板（100）设置成使得第一电路（103）与第一覆盖膜（200）相对，第一层间粘合片（300）位于刚性部分 （700），第二覆盖膜（250）和第二电路基板（150）配置成使得第二电路（153）与第二覆盖膜（250）相对，并执行热压工艺。

    Parallel processor and method of fabrication
    87.
    发明公开
    Parallel processor and method of fabrication 失效
    并行处理器及其制造方法。

    公开(公告)号：EP0637031A3

    公开(公告)日：1996-02-14

    申请号：EP94109624.0

    申请日：1994-06-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Gall, Thomas Patrick ,  Heck, Howard Lincoln ,  Kresge, John Steven

    IPC: G11C5/00

    CPC classification number: H05K3/4635 ,  H05K1/0373 ,  H05K1/0393 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  Y10T29/49126 ,  Y10T29/49155

    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.

    Parallel processor structure and package
    88.
    发明公开
    Parallel processor structure and package 失效
    Parallele Prozessorstruktur und Packung。

    公开(公告)号：EP0637032A2

    公开(公告)日：1995-02-01

    申请号：EP94109625.7

    申请日：1994-06-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Gall, Thomas Patrick ,  Loomis, James Richard

    IPC: G11C5/00

    CPC classification number: H05K3/4691 ,  H05K1/0373 ,  H05K3/4641 ,  H05K2201/015 ,  H05K2201/09109 ,  H05K2201/10159

    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.

    Abstract translation: 各个逻辑和存储元件都在印刷电路板上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构提供互通。 印刷电路卡安装在或连接到多个电路化柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和汽车。 层压部分为处理间，存储器间，处理器间/存储元件和处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路位于单独的印刷电路板和卡上，这些印刷电路板和卡通过电路化的柔性连接，并通过Z轴与其他柔性层通信， 轴向电路（通孔和通孔）。

    Parallel processor and method of fabrication
    89.
    发明公开
    Parallel processor and method of fabrication 失效
    Paralleler Prozessor和Herstellungsverfahren。

    公开(公告)号：EP0637031A2

    公开(公告)日：1995-02-01

    申请号：EP94109624.0

    申请日：1994-06-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Gall, Thomas Patrick ,  Heck, Howard Lincoln ,  Kresge, John Steven

    IPC: G11C5/00

    CPC classification number: H05K3/4635 ,  H05K1/0373 ,  H05K1/0393 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  Y10T29/49126 ,  Y10T29/49155

    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.

    Abstract translation: 一种制造并行处理器结构（11）的方法采用用于Z轴互连的层压开关部分（41）。 集成电路由安装在印刷电路板（25）上并通过电路化的柔性连接器条（21）连接到承载存储器模块（29b）的第二电路板（25）连接的微处理器芯片（29a）组成。 多个这样的集成电路在中央开关部分（41）层叠在一起。 平面电路（214）承载在条带（21）上，并终止于中间部分（211），其中提供通孔（215）用于开关（41）中的条（21）之间的Z轴连接。 带（21）由低热膨胀金属形成的电力平面（221）和信号平面（222）组成，两者均层叠有电介质层（223）。 为了形成开关（41），接合冶金沉积在层压板（21）上，其中两个或更多个在不被不相容的电介质粘合的区域中组装和分离，具有相对较高的第一热转变，并由 在要接合的区域中相对低的第一热转变的相容电介质。 通过加热到接合冶金的共晶温度以上来完成粘结。

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