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    SUB-PACKAGE BYPASS CAPACITOR MOUNTING FOR AN ARRAY PACKAGED INTEGRATED CIRCUIT
    84.
    发明公开
    SUB-PACKAGE BYPASS CAPACITOR MOUNTING FOR AN ARRAY PACKAGED INTEGRATED CIRCUIT 审中-公开
    弥合承载量下外壳组件用于集成电路的MATRIXGEHÄUSTE

    公开(公告)号：EP1175693A1

    公开(公告)日：2002-01-30

    申请号：EP00921552.6

    申请日：2000-03-31

    Applicant: SUN MICROSYSTEMS, INC.

    Inventor： DAVIDSON, Howard, L.

    IPC: H01L21/00

    CPC classification number: H01L23/66 ,  H01L23/642 ,  H01L25/162 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01057 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/112 ,  H05K2201/10325 ,  H05K2201/10545 ,  H05K2201/10704 ,  H05K2201/10734 ,  Y10T29/49128 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: Switching noise within an LGA-packaged or PGA-packaged IC Vdd and IC Vss nodes is reduced by spreading the electrical current in the bypass path to reduce the effective current loop area, and thus reduce the energy stored in the magnetic field surrounding the current path. This result is achieved by minimizing the horizontal components of the linkage paths between the IC nodes to be bypassed and the bypass capacitor. Since effective inductance Leff seen by the bypass capacitor is proportional to magnetic energy, Leff is reduced over a broad band of frequencies. For each bypass capacitor, a pair of conductive vias is formed. A first via is coupled to the LGA package Vcc plane and to the IC Vdd node, and a second via is coupled to the LGA package Vss plane and to the IC Vss node. These vias preferably are spaced-apart a distance ΔX corresponding to the distance between first and second connections on the bypass capacitor although sub-mm offsets in a via at connections may be used to accommodate differing connection pitches. The bypass capacitor connections are coupled to the lower surfaces of the first and second vias, at the lower surface of the LGA package. When the package is inserted into a socket, the bypass capacitor extends into at least some of the otherwise unused recess in the socket. Multiple bypass capacitors are accommodated by forming additional spaced-apart vias that may be electrically parallel-coupled.

    APPARATUS HAVING INNER LAYERS SUPPORTING SURFACE-MOUNT COMPONENTS
    86.
    发明授权
    APPARATUS HAVING INNER LAYERS SUPPORTING SURFACE-MOUNT COMPONENTS 失效
    VORRICHTUNG MITOBERFLÄCHENMONTIERTENBAUTEILEN TRAGENDEN INNENSCHICHTEN

    公开(公告)号：EP0749674B1

    公开(公告)日：1999-01-20

    申请号：EP95913541.9

    申请日：1995-03-09

    Applicant: THE PANDA PROJECT

    Inventor： CRANE, Stanford, W., Jr. ,  PORTUONDO, Maria, M.

    IPC: H05K3/34 ,  H05K3/40

    CPC classification number: H01L23/49861 ,  H01L23/49811 ,  H01L2924/0002 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/308 ,  H05K3/321 ,  H05K3/3421 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2201/10189 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10704 ,  H05K2201/10772 ,  H05K2201/10893 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00 ,  H01L2924/00012

    Abstract: An apparatus comprising a multi-layer substrate (10) including a plurality of layers of insulative material (12), at least one well (15) formed in at least one of the layers, the well (15) extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component (13) formed within the well (15) on the inner surface of the multi-layer substrate; and a device having at least one electrically conductive lead or wire (11) extending into the well (15) and being in direct physical contact with the electrically conductive component (13) formed on the inner surface of the multi-layer substrate. Also, a method of manufacturing an apparatus comprising the steps of forming a multi-layer substrate (10) including a plurality of layers of insulative material (12), at least one well (15) formed in at least one of the layers, the well (15) extending from an outer surface of the multi-layer substrate to an inner surface of the multi-layer substrate, and an electrically conductive component (13) formed within the well (15) on the inner surface of the multi-layer substrate; and extending at least one electrically conductive lead or wire (11) from a device into the well (15) such that the lead or wire is in direct physical contact with the electrically conductive component (13) formed on the inner surface of the multi-layer substrate.

    Abstract translation: 半导体管芯封装（30）包括多个导电引线（11）和用于承载电信号的多层结构（10），所述多层结构（10）包括多层绝缘材料（12a-12d） ），每个层包括在该层的相对侧上的第一表面和第二表面。 每个引线（11）延伸到完全延伸通过至少一个层的对应的阱（15），并且在一个层的一个表面上底部，阱（15）不通过该表面延伸并且电耦合 涉及形成在其对应的井（15）内的导电接合结构（13）。

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