公开(公告)号：US20060005986A1

公开(公告)日：2006-01-12

申请号：US11221137

申请日：2005-09-07

Applicant: David Alcoe

Inventor： David Alcoe

IPC: H02G3/08 ,  B23K31/00

CPC classification number: H05K13/0465 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/10126 ,  H01L2924/01322 ,  H01L2924/09701 ,  H05K3/3436 ,  H05K2201/0133 ,  H05K2201/10265 ,  H05K2201/10977 ,  H05K2203/043 ,  H05K2203/0465 ,  H05K2203/306 ,  Y02P70/613 ,  Y10T29/49204 ,  Y10T29/49211 ,  Y10T29/49213 ,  H01L2924/00014

Abstract: An electronic package includes a substrate having a contact pad thereon, a reformable member such as a solder ball positioned on the contact pad, and an elastic member positioned around the reformable member. The elastic member exerts a girdling force on the reformable member so that when the reformable member is softened, the elastic member elongates the reformable member. This elongation accommodates thermal and other stresses between the foregoing substrate and another substrate joined at the free end of the reformable member. An apparatus is also provided for positioning the elastic member on and around the reformable member.

公开(公告)号：US20050022376A1

公开(公告)日：2005-02-03

申请号：US10630722

申请日：2003-07-31

Applicant: David Alcoe

Inventor： David Alcoe

IPC: G01R31/26 ,  G01R1/04 ,  G01R1/06 ,  H05K3/30 ,  B23P19/00 ,  G01R1/00

CPC classification number: G01R1/0483 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/53174

Abstract: A test apparatus and method in which a compressible housing is used to retain an electronic component having conductors thereon. The compressible housing is lowered onto a suitable base member having upstanding probes which are also compressible and which physically engage respective ones of the conductors at one end thereof and an appropriate conductor (e.g., conductive pads on a printed circuit board) on the other when the test apparatus is fully assembled and testing occurs.

Abstract translation: 一种测试装置和方法，其中使用可压缩壳体来保持其上具有导体的电子部件。 可压缩壳体下降到具有直立探头的合适的基座构件上，该探头也是可压缩的，并且在其一端处物理地接合相应的一个导体，另一端物理地接合另一个导体（例如，印刷电路板上的导电焊盘） 测试装置完全组装并进行测试。

公开(公告)号：US06815837B2

公开(公告)日：2004-11-09

申请号：US10423877

申请日：2003-04-28

Applicant: David Alcoe

Inventor： David Alcoe

IPC: H01L2348

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15312 ,  H01L2924/16195 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3426 ,  H05K3/4602 ,  H05K2201/09454 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T29/49149 ,  H01L2224/0401

Abstract: An electronic package and information handling system utilizing same wherein the package substrate includes an internally conductive layer coupled to an external pad and of a size sufficiently large enough to substantially prevent cracking, separation, etc. of the pad when the pad is subjected to a tensile pressure of about 1.4 grams per square mil or greater.

Abstract translation: 一种利用其的电子封装和信息处理系统，其中封装衬底包括耦合到外部焊盘的内部导电层，并且具有足够大的尺寸以足以基本上防止衬垫经受拉伸时的焊盘的开裂，分离等 约1.4克/平方密度或更大的压力。

公开(公告)号：US07109732B2

公开(公告)日：2006-09-19

申请号：US10630722

申请日：2003-07-31

Applicant: David Alcoe

Inventor： David Alcoe

IPC: G01R1/00

CPC classification number: G01R1/0483 ,  Y10T29/49004 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/53174

Abstract: A test apparatus and method in which a compressible housing is used to retain an electronic component having conductors thereon. The compressible housing is lowered onto a suitable base member having upstanding probes which are also compressible and which physically engage respective ones of the conductors at one end thereof and an appropriate conductor (e.g., conductive pads on a printed circuit board) on the other when the test apparatus is fully assembled and testing occurs.

Abstract translation: 一种测试装置和方法，其中使用可压缩壳体来保持其上具有导体的电子部件。 可压缩壳体下降到具有直立探头的合适的基座构件上，该探头也是可压缩的，并且在其一端处物理地接合相应的一个导体，另一端物理地接合另一个导体（例如，印刷电路板上的导电焊盘） 测试装置完全组装并进行测试。

公开(公告)号：US07087846B2

公开(公告)日：2006-08-08

申请号：US10423972

申请日：2003-04-28

Applicant: David Alcoe

Inventor： David Alcoe

IPC: H01R12/04 ,  H05K1/11 ,  H01R9/00 ,  H05K9/00

CPC classification number: H01L23/49838 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/15312 ,  H01L2924/16195 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/116 ,  H05K3/3426 ,  H05K3/4602 ,  H05K2201/09454 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0979 ,  H05K2201/10318 ,  Y10T29/49149 ,  H01L2224/0401

Abstract: An electronic package and information handling system utilizing same wherein the package substrate includes an internally conductive layer coupled to an external pad to provide reinforced adhesion of the pad to the substrate to substantially prevent cracking, separation, etc. of the pad when the pad has a pin bonded thereto and the package is coupled to an external substrate (e.g., printed circuit board). The reinforced adhesion also prevents pad separation, etc. during periods of package handling, manufacture, etc.

Abstract translation: 一种利用其的电子封装和信息处理系统，其中封装衬底包括耦合到外部焊盘的内部导电层，以便当焊盘具有焊盘时基板防止焊盘的开裂，分离等等 引脚连接到其上并且封装件耦合到外部基板（例如，印刷电路板）。 在包装处理，制造等期间，增强的附着力也防止垫分离等。

公开(公告)号：US07015574B2

公开(公告)日：2006-03-21

申请号：US10495674

申请日：2002-10-25

Applicant: David Alcoe ,  Ronald Nowak ,  Francesco Preda ,  Stefano Sergio Oggioni

Inventor： David Alcoe ,  Ronald Nowak ,  Francesco Preda ,  Stefano Sergio Oggioni

IPC: H01L23/48

CPC classification number: H05K1/0219 ,  H01L23/16 ,  H01L23/36 ,  H01L23/49822 ,  H01L23/66 ,  H01L25/0655 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01057 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/111 ,  H05K2201/09236 ,  H05K2201/09781

Abstract: An electronic device carrier (110) adapted for transmitting high-frequency signals, including a circuitized substrate with a plurality of conductive layers (240a to 240g) insulated from each other, the conductive layers being arranged in a sequence from a first one of the conductive layers (240a) wherein a plurality of signal tracks (200) each one ending with a contact area (205) for transmitting a high-frequency signal are formed, and a reference structure (215a, 215b, 230) connectable to a reference voltage or ground for shielding the signal tracks the reference structure includes at least one reference track (230) formed in a second one of the conductive layers (240b) adjacent to the first conductive layer and at least one further reference track formed in one of the conductive layers (240d) different from the first and second conductive layer, a portion of each signal track excluding at least the area corresponding to the orthographic projection of associated contact area being superimposed in plan view to a corresponding reference track and at least a part of the area corresponding to the orthographic projection of the contact area associated to each signal track being superimposed in plan view to a corresponding further reference track with interposition of a floating conductive track, i.e. a track not connected to any signal, reference voltage or ground track.

Abstract translation: 一种电子设备载体（110），适于传输高频信号，所述高频信号包括具有彼此绝缘的多个导电层（240a至240g）的电路化基板，所述导电层按照以下顺序排列： 形成多个信号轨道（200）的导电层（240a），每个信号轨道（200）各自以用于发送高频信号的接触区域（205）结束，并且参考结构（215a，215b，230）可连接 参考电压或接地用于屏蔽信号轨道，参考结构包括形成在与第一导电层相邻的导电层（240b）中的第二导体层（240b）中的至少一个参考轨道（230）和形成的至少一个另外的参考轨迹 在与第一和第二导电层不同的导电层（240d）之一中，每个信号轨道的一部分至少排除对应于相关联的正交投影的区域 接触区域在平面图中叠加到对应的参考轨道，并且与平面图中叠加的每个信号轨道相关联的接触区域的正交投影对应的区域的至少一部分与相应的另外的参考轨道相互叠加， 导电轨道，即没有连接到任何信号，参考电压或地面轨道的轨道。

公开(公告)号：US20070230130A1

公开(公告)日：2007-10-04

申请号：US11396711

申请日：2006-04-04

Applicant: David Alcoe ,  Varaprasad Calmidi

Inventor： David Alcoe ,  Varaprasad Calmidi

IPC: H05K7/20

CPC classification number: H01L23/3737 ,  H01L23/3735 ,  H01L23/433 ,  H01L24/31 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011

Abstract: An electronic package which includes a substrate (e.g., a chip carrier substrate or a PCB), an electronic component (e.g., a semiconductor chip), a heatsink and a thermal interposer for effectively transferring heat from the chip to the heatsink. The interposer includes a compressible, resilient member (e.g., an elastomeric pad) and a plurality of thin, metallic sheets (e.g., copper foils) and the thickness thereof can be adjusted by altering the number of such foils.

Abstract translation: 包括衬底（例如，芯片载体衬底或PCB），电子部件（例如，半导体芯片），散热器和热插入件的电子封装件，用于将热量从芯片有效地传递到散热器。 插入器包括可压缩的弹性构件（例如，弹性垫）和多个薄的金属片（例如铜箔），并且其厚度可以通过改变这种箔的数量来调节。

公开(公告)号：US20050099783A1

公开(公告)日：2005-05-12

申请号：US11011868

申请日：2004-12-14

Applicant: David Alcoe ,  Kim Blackwell

Inventor： David Alcoe ,  Kim Blackwell

IPC: H01L23/498 ,  H05K3/46 ,  H05K1/00 ,  H05K1/03

CPC classification number: H01L24/16 ,  H01L23/49822 ,  H01L24/17 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/09536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method and structure for forming an electronic structure that comprises a redistribution structure on a circuitized substrate. The redistribution structure includes N dielectric layers (N≧2) and N metal planes formed in the following sequence: dielectric layer 1 on a metallic plane that exists on a surface of the substrate, metal plane 1 on dielectric layer 1, dielectric layer 2 on dielectric layer 1 and metal plane 1, metal plane 2 on the dielectric layer 2, . . . , dielectric layer N on dielectric layer N-1 and metal plane N-1, and metal plane N on the dielectric layer N. Metal planes or metallic planes may include signal planes, power planes, ground planes, etc. A microvia structure, which is formed through the N dielectric layers and electrically couples metal plane N to the metallic plane, includes a microvia or a portion of a microvia through each dielectric layer.

Abstract translation: 一种用于形成电子结构的方法和结构，其包括在电路化基板上的再分布结构。 再分布结构包括N个介电层（N> = 2）和以下列顺序形成的N个金属平面：存在于基板表面上的金属平面上的电介质层1，电介质层1上的金属平面1，电介质层2 在电介质层1和金属平面1上，电介质层2上的金属平面2。 。 。 介电层N 1上的电介质层N和金属平面N 1以及电介质层N上的金属平面N.金属平面或金属平面可以包括信号面，电力平面，接地面等。微孔结构 通过N个介电层形成并将金属平面N电耦合到金属平面，包括通过每个电介质层的微孔或微孔的一部分。