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公开(公告)号：US09867290B2
公开(公告)日：2018-01-09
申请号：US14834205
申请日：2015-08-24
Applicant: Multek Technologies Ltd.
Inventor： Kwan Pen , Pui Yin Yu
CPC classification number: H05K1/115 , H05K1/0216 , H05K1/0298 , H05K1/112 , H05K3/0058 , H05K3/06 , H05K3/181 , H05K3/188 , H05K3/42 , H05K3/422 , H05K3/424 , H05K3/429 , H05K3/4602 , H05K3/4623 , H05K3/4638 , H05K2201/095 , H05K2201/09545 , H05K2201/09554 , H05K2201/10303
Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.
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公开(公告)号：US09549463B1
公开(公告)日：2017-01-17
申请号：US14712823
申请日：2015-05-14
Applicant: Multek Technologies, Ltd
Inventor： Joan K. Vrtis , Michael James Glickman , Mark Bergman , Shurui Shang
CPC classification number: H05K1/0281 , H05K1/0283 , H05K3/24
Abstract: A circuit board comprises one or more rigid sections, one or more flexible sections, and one or more transition areas where the circuit board transitions from the rigid section to the flexible section. One or more mechanically restrictive components are applied at a transition area to prevent failure and/or breakage of the circuit as it is bent and flexed. The mechanically restrictive components can be dispersed throughout the circuit as a coverlay, an underlay, and symmetrically positioned within the circuit board as an overlay and an underlay.
Abstract translation: 电路板包括一个或多个刚性部分，一个或多个柔性部分以及电路板从刚性部分转变到柔性部分的一个或多个过渡区域。 在过渡区域施加一个或多个机械限制部件，以防止电路在弯曲和弯曲时的故障和/或破损。 机械限制部件可以作为覆盖层，底板分散在整个电路中，并且作为覆盖层和底层被对称地定位在电路板内。
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公开(公告)号：US20160278208A1
公开(公告)日：2016-09-22
申请号：US14834205
申请日：2015-08-24
Applicant: Multek Technologies Ltd.
Inventor： Kwan Pen , Pui Yin Yu
CPC classification number: H05K1/115 , H05K1/0216 , H05K1/0298 , H05K1/112 , H05K3/0058 , H05K3/06 , H05K3/181 , H05K3/188 , H05K3/42 , H05K3/422 , H05K3/424 , H05K3/429 , H05K3/4602 , H05K3/4623 , H05K3/4638 , H05K2201/095 , H05K2201/09545 , H05K2201/09554 , H05K2201/10303
Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is applied to a conductive layer of an inner core and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the plug non-conductive layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.
Abstract translation: 用于制造电路板的选择性段通过电镀工艺选择性地将内部导电层互连在相同的通孔内的单独的段。 将电镀抗蚀剂施加到内芯的导电层，然后在无电镀处理之后剥离。 在电镀抗蚀剂上剥离化学镀导致通孔壁上的电镀不连续。 在随后的电镀工艺中，由于电镀不连续性，插头非导电层不能镀覆。 所得到的电路板结构在通孔内具有单独的电互连段。
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公开(公告)号：US09763327B2
公开(公告)日：2017-09-12
申请号：US14834180
申请日：2015-08-24
Applicant: Multek Technologies Ltd.
Inventor： Kwan Pen , Pui Yin Yu
CPC classification number: H05K1/115 , H05K1/0216 , H05K1/0298 , H05K1/112 , H05K3/0058 , H05K3/06 , H05K3/181 , H05K3/188 , H05K3/42 , H05K3/422 , H05K3/424 , H05K3/429 , H05K3/4602 , H05K3/4623 , H05K3/4638 , H05K2201/095 , H05K2201/09545 , H05K2201/09554 , H05K2201/10303
Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.
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公开(公告)号：US09723713B1
公开(公告)日：2017-08-01
申请号：US14712842
申请日：2015-05-14
Applicant: Multek Technologies, Ltd
Inventor： Joan K. Vrtis , Michael James Glickman , Mark Bergman , Shurui Shang
CPC classification number: H05K1/0281 , H05K1/0278 , H05K1/028 , H05K1/0283 , H05K1/147 , H05K1/148 , H05K3/4691 , H05K2201/2009
Abstract: In order to limit the stress and strain applied to a printed circuit board while still maintaining flexibility, a flexible section of the printed circuit board is configured to have a non-linear portion that functions as a hinge when the flexible section is bent, flexed, twisted or otherwise subjected to a motion related force. The hinge configuration improves durability and flexibility while minimizing ripping and cracking of the printed circuit board, particularly interconnects within the flexible section and a transition region between the flexible section and a rigid section of the printed circuit board. The hinge is configured to have a non-linear shape, such as a serpentine or circuitous path that can include curved portions, different linear portions or some combination of curved and linear portions.
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Patent Agency Ranking
公开(公告)号：US09659478B1
公开(公告)日：2017-05-23
申请号：US14572610
申请日：2014-12-16
Applicant: Multek Technologies Ltd.
Inventor： Mark Bergman , Michael James Glickman
CPC classification number: H05K3/42 , G01M5/0041 , G01M5/0083 , G06F1/16 , G08B21/182 , G08B23/00 , H05K1/0201 , H05K1/115 , H05K2201/0302 , H05K2203/0338 , H05K2203/0723
Abstract: A stress and/or strain indicator comprises a wearable body, one or more flexible sections, one or more rigid sections and one or more strain gauges. The one or more strain gauges detect a level of stress and/or strain applied to the wearable body in order to indicate when the product is in danger of failing. A warning is activated based upon the level of stress and/or strain applied to the wearable body. For example, the stress and/or strain indicator is able to display a visual and/or an audible warning that a high level of stress and/or strain has been applied to the wearable body and the product is in danger of failing. In some embodiments, the stress and/or strain incident is recorded and downloadable. Consequently, a user is better informed as to when the electronic product is in danger of failing because of damage or misuse.
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公开(公告)号：US10449729B1
公开(公告)日：2019-10-22
申请号：US14958603
申请日：2015-12-03
Applicant: Multek Technologies Ltd.
Inventor： Michael James Glickman , Jennet Ellen Johnson
Abstract: A 3D printing system includes a 3D printer configured to receive as input a coated or un-coated optical fiber, to coat the optical fiber in the case of an input un-coated optical fiber, to treat an outer coating of the coated optical fiber, and to precisely output the coated optical fiber onto a specific location on a substrate such that the coated optical fiber is securely attached to the substrate via the treated outer coating. The 3D printer has a nozzle head that includes treating element for treating, such as heating or curing, the outer coating of the coated optical fiber. The 3D printer also includes a movement mechanism, such as an XYZ gantry, coupled to the nozzle head such that the nozzle head can be precisely moved relative to the substrate for well controlled placement of the treated coated optical fiber on the substrate.
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公开(公告)号：US10015880B1
公开(公告)日：2018-07-03
申请号：US14565227
申请日：2014-12-09
Applicant: Multek Technologies Ltd.
Inventor： Mark Bergman , Joan K. Vrtis
CPC classification number: H05K1/0271 , H05K1/0278 , H05K1/028 , H05K1/0281 , H05K1/0283 , H05K1/038 , H05K1/0386 , H05K1/0393 , H05K1/144 , H05K1/148 , H05K3/22 , H05K3/4691 , H05K2201/0137 , H05K2201/05 , H05K2201/058 , H05K2201/09945 , H05K2201/0999 , H05K2201/2009
Abstract: A rip stop material is attached at a stress area of a flexible circuit board in order to strengthen the flexible circuit board and minimize ripping and cracking in the polyimide and/or the copper conductors of the circuit. A rip stop transition layer is formed and deposited at a location on the flexible circuit in order to minimize, reduce, if not preventing cracking and ripping of the circuit as it is bent and flexed. The rip stop transition layer can be placed at different locations on and within the flexible circuit in order to minimize cracking and ripping as the flexible circuit is bent, flexed and twisted.
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公开(公告)号：US09560746B1
公开(公告)日：2017-01-31
申请号：US14604476
申请日：2015-01-23
Applicant: Multek Technologies, Ltd.
Inventor： Mark Bergman , Michael James Glickman
CPC classification number: H05K1/189 , H05K2201/0154 , H05K2201/10378 , H05K2201/2009
Abstract: In order to limit the stress and strain applied to a printed circuit board while still maintaining flexibility, multiple small rigid mesas are formed on a flexible printed circuit, where the rigid mesas are physically isolated by trenches formed around their perimeters. Individual electronic components are attached to the multiple rigid mesas. These trenches form openings at which the printed circuit board is enabled to flex, bend or twist, thereby minimizing, if not eliminating, resulting stress applied to the interconnection between the electronic components and the rigid mesas.
Abstract translation: 为了限制施加到印刷电路板上的应力和应变同时仍然保持柔性，在柔性印刷电路上形成多个小的刚性台面，其中刚性台面通过围绕其周边形成的沟槽物理隔离。 单独的电子部件连接到多个刚性台面。 这些沟槽形成开口，印刷电路板在该开口处能够弯曲，弯曲或扭曲，从而最小化（如果不消除）施加到电子部件和刚性台面之间的互连的所产生的应力。
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10.发明授权公开(公告)号：US09521748B1
公开(公告)日：2016-12-13
申请号：US14565267
申请日：2014-12-09
Applicant: Multek Technologies Ltd.
Inventor： Mark Bergman , Joan K. Vrtis
CPC classification number: H05K1/0271 , H05K1/0278 , H05K1/028 , H05K1/0281 , H05K1/0283 , H05K1/038 , H05K1/0386 , H05K1/0393 , H05K1/144 , H05K1/148 , H05K3/22 , H05K3/4691 , H05K2201/0137 , H05K2201/05 , H05K2201/058 , H05K2201/09945 , H05K2201/0999 , H05K2201/2009
Abstract: Mechanical measures strengthen a flexible circuit board or deformable electronic by manipulating the location and/or intensity of the stress concentration or to limit bending, torsion, and stretching. A material layer is patterned onto the flexible circuit board with a specific pattern and place of deposition in order to modify the stress concentration and profile of the circuit board and increase its overall strength. The material layer may be configured to modify the stress concentrations during bending away from the weak points in the assembly or to spread the stress during bending by increasing the radius of the bend curvature and therefore decreasing the chance of mechanical failure.
Abstract translation: 机械措施通过操纵应力集中的位置和/或强度或限制弯曲，扭转和拉伸来加强柔性电路板或可变形电子。 将材料层图案化到具有特定图案和沉积位置的柔性电路板上，以便改变电路板的应力集中和轮廓并增加其整体强度。 材料层可以被配置为在远离组件中的弱点的过程中修改弯曲期间的应力集中，或者通过增加弯曲曲率半径来扩展弯曲过程中的应力，从而降低机械故障的机会。
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