公开(公告)号：WO2009124785A1

公开(公告)日：2009-10-15

申请号：PCT/EP2009/050585

申请日：2009-01-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  SRI-JAYANTHA, Sri ,  RUSSELL, David, John ,  KACKER, Karan ,  QUESTAD, David ,  POWELL, Douglas, Oliver

Inventor： SRI-JAYANTHA, Sri ,  RUSSELL, David, John ,  KACKER, Karan ,  QUESTAD, David ,  POWELL, Douglas, Oliver

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49822 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/10253 ,  H01L2924/15311

Abstract: A substrate via structure for stacked vias includes: a plurality of stacked vias, wherein each via is disposed on a landing; and at least one constrainer disc surrounding at least one via, for constraining in-plane deformation of the substrate via structure. The constrainer disc is embedded such that the constrainer disc is disposed between two layers of resin. The constrainer discs may be made of copper. The constrainer disc may be circular or square-shaped. Preferably there is a dielectric gap between the constrainer disc and the via.

Abstract translation: 用于堆叠通孔的衬底通孔结构包括：多个堆叠的通孔，其中每个通孔设置在层站上; 以及围绕至少一个通孔的至少一个约束盘，用于限制基板经由结构的平面内变形。 约束盘被嵌入，使得约束盘设置在两层树脂之间。 约束盘可以由铜制成。 约束盘可以是圆形或正方形。 优选地，在约束盘和通孔之间存在电介质间隙。

公开(公告)号：WO2009092677A2

公开(公告)日：2009-07-30

申请号：PCT/EP2009050524

申请日：2009-01-19

Applicant: IBM ,  IBM UK ,  KACKER KARAN ,  POWELL DOUGLAS OLIVER ,  QUESTAD DAVID ,  RUSSELL DAVID JOHN ,  SRI-JAYANTHA SRI

Inventor： KACKER KARAN ,  POWELL DOUGLAS OLIVER ,  QUESTAD DAVID ,  RUSSELL DAVID JOHN ,  SRI-JAYANTHA SRI

IPC: H01L23/498

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a plated through hole landing supporting the plurality of stacked vias. The plated through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the plated through hole landing.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠通孔的电镀通孔着落。 电镀通孔着色包括顺应中心区; 以及用于连接电镀通孔底板的顺应中心区域的弹簧状刚度减小连接器。

公开(公告)号：WO2009092677A3

公开(公告)日：2009-07-30

申请号：PCT/EP2009/050524

申请日：2009-01-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED ,  KACKER, Karan ,  POWELL, Douglas, Oliver ,  QUESTAD, David ,  RUSSELL, David, John ,  SRI-JAYANTHA, Sri

Inventor： KACKER, Karan ,  POWELL, Douglas, Oliver ,  QUESTAD, David ,  RUSSELL, David, John ,  SRI-JAYANTHA, Sri

IPC: H01L23/498

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a plated through hole landing supporting the plurality of stacked vias. The plated through hole landing includes a compliant center zone; and spring-like stiffness-reducing connectors for connecting the compliant center zone of the plated through hole landing.

公开(公告)号：WO2013074178A1

公开(公告)日：2013-05-23

申请号：PCT/US2012/052749

申请日：2012-08-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  QUESTAD, David, L. ,  SAUTER, Wolfgang ,  SULLIVAN, Timothy, D.

Inventor： DAUBENSPECK, Timothy, H. ,  GAMBINO, Jeffrey, P. ,  MUZZY, Christopher, D. ,  QUESTAD, David, L. ,  SAUTER, Wolfgang ,  SULLIVAN, Timothy, D.

IPC: H01L23/48

CPC classification number: H01L23/3171 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02126 ,  H01L2224/02235 ,  H01L2224/0401 ,  H01L2224/05019 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05552 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/0612 ,  H01L2224/06131 ,  H01L2224/13007 ,  H01L2224/13017 ,  H01L2224/13027 ,  H01L2224/13111 ,  H01L2224/1312 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2924/00 ,  H01L2924/15311 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/00012

Abstract: A topographical feature (305) is formed proximate to a conductive bond pad (235) that is used to couple a solder bump (160) to a semiconductor die (140). The topographical feature (305) is separated from the conductive bond pad (235) by a gap (310). In one embodiment, the topographical feature (305) is formed at a location that is slightly beyond the perimeter of the solder bump (160), wherein an edge of the bump (160) is aligned vertically to coincide with the gap (310) separating the conductive bond pad (235) from the topographical feature (305). The topographical feature (305) provides thickness enhancement of a non-conductive layer (240) disposed over the semiconductor die (140) and the conductive bond pad (235) and stress buffering.

Abstract translation: 形成靠近用于将焊料凸块（160）耦合到半导体管芯（140）的导电接合焊盘（235）的形貌特征（305）。 地形特征（305）通过间隙（310）与导电接合垫（235）分离。 在一个实施例中，形貌特征（305）形成在稍微超过焊料凸块（160）的周边的位置处，其中凸起（160）的边缘垂直对准，以与间隔（310）分离重合 来自所述形貌特征（305）的所述导电接合焊盘（235）。 形貌特征（305）提供设置在半导体管芯（140）和导电接合焊盘（235）之上的非导电层（240）的厚度增强和应力缓冲。

公开(公告)号：WO2009020911A1

公开(公告)日：2009-02-12

申请号：PCT/US2008/072089

申请日：2008-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BROFMAN, Peter, J. ,  CASEY, Jon, A. ,  MELVILLE, Ian, D. ,  QUESTAD, David, L. ,  SAUTER, Wolfgang ,  WASSICK, Thomas, A.

Inventor： BROFMAN, Peter, J. ,  CASEY, Jon, A. ,  MELVILLE, Ian, D. ,  QUESTAD, David, L. ,  SAUTER, Wolfgang ,  WASSICK, Thomas, A.

IPC: H01L23/28

CPC classification number: H01L21/563 ,  H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2224/73203 ,  H01L2924/01057

Abstract: Structures and a method for forming the same. The structure includes a semiconductor substrate (11), a transistor (11a, 11b, 11c) on the semiconductor substrate, and N interconnect layers (13) on top of the semiconductor substrate (11), N being a positive integer. The transistor (11a, 11b, 11c) is electrically coupled to the N interconnect layers (13). The structure further includes a first dielectric layer (13d) on top of the N interconnect layers (13) and P crack stop regions (130a-e) on top of the first dielectric layer (120), P being a positive integer. The structure further includes a second dielectric layer (140) on top of the first dielectric layer. Each crack stop region (130a-c) of the P crack stop regions (130a-e) is completely surrounded by the first dielectric layer (120) and the second dielectric layer (130). The structure further includes an underfill layer (190) on top of the second dielectric layer (130). The second dielectric layer (130) is sandwiched between the first dielectric layer (120) and the underfill layer (190).

Abstract translation: 结构及其形成方法。 该结构包括半导体衬底（11），半导体衬底上的晶体管（11a，11b，11c）和位于半导体衬底（11）顶部的N个互连层（13），N为正整数。 晶体管（11a，11b，11c）电耦合到N个互连层（13）。 所述结构还包括在所述N个互连层（13）的顶部上的第一介电层（13d）和在所述第一介电层（120）的顶部上的P裂缝停止区域（130a-e），P是正整数。 该结构还包括在第一电介质层的顶部上的第二介电层（140）。 P裂纹停止区域（130a-e）的每个裂纹停止区域（130a-c）被第一介电层（120）和第二介电层（130）完全包围。 该结构还包括在第二介电层（130）的顶部上的底部填充层（190）。 第二电介质层（130）夹在第一介电层（120）和底部填充层（190）之间。