公开(公告)号：KR101965957B1

公开(公告)日：2019-04-04

申请号：KR1020170081202

申请日：2017-06-27

Applicant: 도쿄엘렉트론가부시키가이샤

Inventor： 도시마히로유키 ,  시마다아츠시 ,  히라사와다츠오 ,  하타노다츠오 ,  후루카와신지

IPC: H01L21/768 ,  H01L21/324

公开(公告)号：KR101739613B1

公开(公告)日：2017-05-24

申请号：KR1020130154357

申请日：2013-12-12

Applicant: 도쿄엘렉트론가부시키가이샤

Inventor： 이시자카다다히로 ,  스즈키겐지 ,  시마다아츠시

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H05K3/107 ,  C23C14/358 ,  H01L21/02063 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/0338 ,  H01L2924/00

Abstract: 본발명은충분한매립성을확보하면서, Cu 배선의저저항화를실현할수 있는 Cu 배선의형성방법에관한것이다. 표면에소정패턴의트렌치가형성된 Si 함유막인층간절연막을가지는웨이퍼에대하여, 트렌치를매립하는 Cu 배선을형성하는 Cu 배선의형성방법으로서, 적어도트렌치의표면에, 하지와의반응에서자기정합배리어막이되는 Mn막을 CVD에의해형성하는공정과, Cu막을 PVD에의해형성하여트렌치내에 Cu막을매립하는공정과, CMP에의해전체면을연마하여트렌치내에 Cu 배선을형성하는공정을포함한다.

公开(公告)号：KR1020140076514A

公开(公告)日：2014-06-20

申请号：KR1020130154357

申请日：2013-12-12

Applicant: 도쿄엘렉트론가부시키가이샤

Inventor： 이시자카다다히로 ,  스즈키겐지 ,  시마다아츠시

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/02 ,  H01L21/3105

CPC classification number: H05K3/107 ,  C23C14/358 ,  H01L21/02063 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76846 ,  H01L21/76855 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K2201/0338 ,  H01L2924/01029 ,  H01L2924/00

Abstract: The present invention relates to a method of forming a copper wire which is capable of making the copper wire have low resistance while sufficiently embedding the copper wire. A method of forming a copper wire by embedding a trench in a wafer including an interlayer dielectric layer containing Si and having a trench of a predetermined pattern formed on a surface of the interlayer dielectric layer, includes the following processes of forming a Mn layer at least on a surface of the trench through CVD, wherein the Mn layer serves as a self-aligned barrier layer in reaction with a substrate; embedding a copper layer formed through PVD in the trench; and forming the copper wire in the trench by polishing an entire surface through CMP.

Abstract translation: 铜线形成方法技术领域本发明涉及能够使铜线充分嵌入铜线时具有低电阻的铜线形成方法。 通过在包括含有Si并具有形成在层间电介质层的表面上的具有预定图案的沟槽的层间电介质层的晶片中嵌入沟槽来形成铜线的方法包括以下至少形成Mn层的方法 通过CVD在沟槽的表面上，其中Mn层用作与衬底反应的自对准阻挡层; 在沟槽中嵌入通过PVD形成的铜层; 以及通过CMP抛光整个表面在沟槽中形成铜线。