公开(公告)号：KR1020070097721A

公开(公告)日：2007-10-05

申请号：KR1020060028330

申请日：2006-03-29

Applicant: 삼성전기주식회사

Inventor： 오카베,슈히치 ,  류창섭 ,  강명삼 ,  박정현 ,  정회구 ,  김지은

IPC: H01L23/12

CPC classification number: H01L2224/81 ,  H01L21/563 ,  H01L23/481 ,  H01L23/4828

Abstract: A substrate for mounting a flip chip and a manufacturing method thereof are provided to prevent copper migration generated in a micro patterning circuit by burying a circuit pattern in an insulator. A method for manufacturing a substrate for mounting a flip chip includes the steps of: laminating a buried pattern substrate with a circuit pattern formed on the surface of a seed layer, on a core substrate having an insulating layer so that the circuit pattern faces the core substrate(100); forming a via hole by punching the seed layer, or the seed layer and a part of the core substrate(110); charging the via hole with conductive paste(130); and removing the seed layer(140). The step of forming a via hole includes the steps of: laminating a dry film on the surface of the seed layer(112); removing a part of the dry film corresponding to a position in which the via hole is formed(114); etching the seed layer of the position in which the dry film is removed(116); peeling off the remaining dry film on the surface of the seed layer(118); and removing the insulator by punching the via hole and exposing the inner layer circuit(120).

Abstract translation: 提供了一种用于安装倒装芯片的基板及其制造方法，以通过将电路图案埋入绝缘体来防止在微图案化电路中产生的铜迁移。 一种用于制造用于安装倒装芯片的基板的方法包括以下步骤：在具有绝缘层的芯基板上层叠具有形成在晶种层表面上的电路图案的掩埋图案基板，使得电路图案面向芯 基板（100）; 通过冲压种子层或种子层和芯基板（110）的一部分来形成通孔; 用导电膏（130）对通孔充电; 以及去除种子层（140）。 形成通孔的步骤包括以下步骤：在种子层（112）的表面上层叠干膜; 去除与形成通孔的位置相对应的干膜的一部分（114）; 蚀刻去除干膜的位置的种子层（116）; 剥离种子层（118）表面上的剩余干膜; 以及通过冲压所述通孔并暴露所述内层电路（120）来去除所述绝缘体。

公开(公告)号：KR100726239B1

公开(公告)日：2007-06-08

申请号：KR1020060071699

申请日：2006-07-28

Applicant: 삼성전기주식회사

Inventor： 김지은 ,  박정현 ,  정회구 ,  강명삼

IPC: H05K3/46

Abstract: A manufacturing method of an electric chip embedded multi-layer PCB(Printed Circuit Board) is provided to improve precision of PCB manufacture by securing a thickness tolerance of a cavity. A manufacturing method of an electric chip embedded multi-layer PCB includes the steps of: selectively laminating a first photoresist corresponding to a position where the electric chip is embedded, on a core substrate having an inner layer circuit on a surface(100); laminating a first buildup layer having a first outer layer circuit on a surface, on the core substrate(120); selectively removing the first buildup layer corresponding to the position where the electric chip is embedded, and forming a cavity by removing the first photoresist(140); and embedding the electric chip in the cavity, and laminating a second buildup layer having the second outer layer circuit on a surface, on the first buildup layer.

Abstract translation: 提供一种电芯片嵌入式多层PCB（印刷电路板）的制造方法，通过确保腔体的厚度公差来提高PCB制造的精度。 一种嵌入电芯片的多层PCB的制造方法，包括以下步骤：在表面（100）上的具有内层电路的芯基板上选择性地层叠与嵌入电芯片的位置对应的第一光刻胶; 在所述核心基板（120）上的表面上层压具有第一外层电路的第一堆积层; 选择性地去除与嵌入电芯片的位置相对应的第一堆积层，并且通过去除第一光致抗蚀剂（140）来形成空腔; 以及将电芯片嵌入腔中，并且在第一堆积层上的表面上层叠具有第二外层电路的第二堆积层。

公开(公告)号：KR100685177B1

公开(公告)日：2007-02-22

申请号：KR1020060022844

申请日：2006-03-10

Applicant: 삼성전기주식회사

Inventor： 강명삼 ,  류창섭 ,  박정현 ,  정회구 ,  김지은

IPC: H01L23/02

公开(公告)号：KR1020070001408A

公开(公告)日：2007-01-04

申请号：KR1020050056882

申请日：2005-06-29

Applicant: 삼성전기주식회사

Inventor： 정회구 ,  이종진 ,  최재민 ,  강명삼 ,  박정현

IPC: H05K3/46

CPC classification number: H05K3/4697 ,  H05K3/0044 ,  H05K3/022 ,  H05K3/4038 ,  H05K3/4602 ,  H05K2201/0145

Abstract: A manufacturing method of a printed circuit board for mounting a chip is provided to realize a miniaturization, lightness, and slimness of product by mounting more than one chip on a manufactured cavity. A manufacturing method of a printed circuit board for mounting a chip includes the steps of: preparing a core on which a predetermined circuit pattern is formed(S100); laminating an insulation layer on an upper face of the core, wherein an opening unit is formed at the insulation layer, corresponding to a chip intended to be mounted(S110); forming a cavity using the opening unit and the core upper face by laminating a thermoplastic film on an upper face of the insulation layer and thermally pressurizing the thermoplastic film(S120); removing the thermoplastic film(S130); and forming an upper circuit pattern on the upper face of the insulation layer, corresponding to the predetermined circuit pattern(S140). Wherein, in the third step, a shape of the cavity is maintained by filling an inside of the cavity with the molten thermoplastic film.

Abstract translation: 提供了一种用于安装芯片的印刷电路板的制造方法，以通过在制造的腔体上安装多于一个的芯片来实现产品的小型化，轻量化和薄型化。 用于安装芯片的印刷电路板的制造方法包括以下步骤：制备其上形成有预定电路图案的芯（S100）; 在所述芯的上表面上层压绝缘层，其中在所述绝缘层处形成开口单元，对应于要安装的芯片（S110）; 通过在所述绝缘层的上表面层叠热塑性膜并对所述热塑性膜进行热加压来形成使用所述开口单元和所述芯上表面的空腔（S120）。 去除热塑性薄膜（S130）; 以及在所述绝缘层的上表面上形成对应于所述预定电路图案的上电路图案（S140）。 其中，在第三步骤中，通过用熔融的热塑性膜填充空腔的内部来保持空腔的形状。

公开(公告)号：KR100661295B1

公开(公告)日：2006-12-26

申请号：KR1020060014561

申请日：2006-02-15

Applicant: 삼성전기주식회사

Inventor： 박정현 ,  류창섭 ,  정회구 ,  김지은 ,  강명삼

IPC: H05K3/22

Abstract: A package PCB(Printed Circuit Board) and a manufacturing method thereof are provided to improve strength of a core board by embedding a circuit pattern inside the core board. A package PCB includes a core board(42), a metal plate(41), a circuit pattern(43), and a via-hole(45). The metal plates are symmetrically laminated on both surfaces of the core board. Plural punch holes are formed on the metal plate. The circuit pattern is formed on a surface of the core board, which corresponds to the punch holes. The via-hole electrically couples the circuit patterns with each other. The circuit pattern is arranged not to be protruded from a surface of the core board. A surface of the circuit pattern is exposed. The core board is a single insulation layer.

Abstract translation: 提供封装PCB（印刷电路板）及其制造方法，以通过在芯板内嵌入电路图案来提高芯板的强度。 封装PCB包括核心板（42），金属板（41），电路图案（43）和通孔（45）。 金属板对称地层压在核心板的两个表面上。 在金属板上形成多个冲孔。 电路图案形成在核心板的与冲孔对应的表面上。 通孔将电路图案彼此电耦合。 电路图案布置为不从核心板的表面突出。 电路图案的表面被暴露。 核心板是单层绝缘层。

公开(公告)号：KR100836653B1

公开(公告)日：2008-06-10

申请号：KR1020060104203

申请日：2006-10-25

Applicant: 삼성전기주식회사

Inventor： 오카베,슈히치 ,  강명삼 ,  박정현 ,  정회구 ,  박정우 ,  김지은

IPC: H05K3/20

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: 회로기판 및 그 제조방법 개시된다. (a) 시드층이 적층된 캐리어의 시드층에, 제1 회로패턴에 상응하도록 제1 도금층, 제1 금속층 및 제2 도금층이 순차적으로 적층되는 도전성 양각패턴을 형성하는 단계, (b) 도전성 양각패턴이 형성되는 캐리어의 일면과 절연체의 일면이 대향하도록 적층하고 압착하는 단계, (c) 캐리어를 제거하여 시드층 및 도전성 양각패턴을 절연체에 전사하는 단계, (d) 절연체의 일면에 전사된 시드층에, 제2 회로패턴에 상응하도록 제3 도금층 및 제2 금속층이 순차적으로 적층되는 도전패턴을 형성하는 단계, (e) 제1 도금층 및 시드층을 제거하는 단계 및 (f) 제1 금속층 및 제2 금속층을 제거하는 단계를 포함하는 회로기판 제조방법은, 절연체의 증가 없이 절연체에 매립되는 회로패턴 및 절연체의 외층에 형성되는 회로패턴의 2중의 회로패턴을 형성하여 고밀도 회로패턴을 갖는 회로기판을 제조할 수 있다
회로기판, 금속층, 도금층, 매립

公开(公告)号：KR100796981B1

公开(公告)日：2008-01-22

申请号：KR1020060101632

申请日：2006-10-19

Applicant: 삼성전기주식회사

Inventor： 박정우 ,  강명삼 ,  박정현 ,  김지은 ,  최종규 ,  김상덕 ,  정회구

IPC: H05K3/46

CPC classification number: H05K3/4007 ,  H05K3/007 ,  H05K3/1258

Abstract: A method for manufacturing a printed circuit board is provided to simplify a process and prevent a void between a pattern and an insulation layer from occurring by reducing the height difference of the rest part except for a bump. A method for manufacturing a printed circuit board includes the steps of: forming engraved patterns corresponding to bumps on a carrier(S10); stacking on the carrier masks having opening units corresponding to the engraved patterns(S11); forming the bumps by charging a conductive paste on the engraved patterns(S20); stacking the carrier formed thereon the bump on one surface or both surfaces of a substrate so as to transfer the bumps to the substrate(S30); exposing the bumps by removing the carrier(S40); and stacking a first insulation layer on the one surface or the both surfaces of the substrate(S50).

Abstract translation: 提供了一种用于制造印刷电路板的方法，以简化工艺并通过减小除了凸起之外的其余部分的高度差来防止图案和绝缘层之间的空隙。 制造印刷电路板的方法包括以下步骤：形成与载体上的凸起相对应的雕刻图案（S10）; 堆叠在具有对应于雕刻图案的开口单元的载体掩模上（S11）; 通过在雕刻图案上充电导电膏来形成凸块（S20）; 将形成在其上的载体堆叠在基板的一个表面或两个表面上，以将凸块传送到基板（S30）; 通过移除载体来暴露凸起（S40）; 并在基板的一个表面或两个表面上层叠第一绝缘层（S50）。

公开(公告)号：KR100782412B1

公开(公告)日：2007-12-05

申请号：KR1020060104205

申请日：2006-10-25

Applicant: 삼성전기주식회사

Inventor： 김상덕 ,  박정현 ,  정회구 ,  최종규 ,  김지은 ,  박정우

IPC: H01L21/027

CPC classification number: H05K3/20 ,  H05K3/205 ,  H05K3/207 ,  H05K3/386 ,  H05K2203/0113 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49163 ,  H05K3/202

Abstract: A method for forming a transcriptional circuit and a method for manufacturing a circuit board are provided to reduce a manufacturing cost by implementing the transcriptional circuit on an insulation substrate using conventional equipment. A resist film is selectively formed on a mold substrate such that engraved patterns corresponding to circuit patterns are formed(S100). Photoresist film layer is stacked on the mold substrate(S110). The photoresist film layer is selectively exposed and developed(S120). A separation layer is formed on the engraved patterns(S200). A conductive material is formed on the engraved patterns(S300). By pressing a carrier, which is opposite to the mold substrate including the conductive material, the conductive material is transferred to the carrier(S400).

Abstract translation: 提供了一种形成转录电路的方法和电路板的制造方法，以通过使用常规设备在绝缘基板上实施转录电路来降低制造成本。 在模具基板上选择性地形成抗蚀剂膜，从而形成对应于电路图案的雕刻图案（S100）。 光致抗蚀剂膜层堆叠在模具基板上（S110）。 光致抗蚀剂膜层被选择性地曝光和显影（S120）。 在雕刻图案上形成分离层（S200）。 在雕刻图案上形成导电材料（S300）。 通过按压与包括导电材料的模具基板相对的载体，导电材料被转移到载体（S400）。

公开(公告)号：KR100749141B1

公开(公告)日：2007-08-14

申请号：KR1020060002950

申请日：2006-01-11

Applicant: 삼성전기주식회사

Inventor： 김지은 ,  강명삼 ,  박정현 ,  정회구

IPC: H01L23/12

Abstract: A POP(Package On Package) substrate and its manufacturing method are provided to increase the number of integrated chips without the increase of thickness by extending the distance between a top package and a bottom package using a metal bump and cavity of the bottom package. An inner circuit(12) is formed on a surface of a core substrate(10). A metal plate with a circuit pattern corresponding to an outer circuit(52) is formed on the surface of the core substrate via an insulating member(40). At this time, the circuit pattern is opposite to the inner circuit. A portion of the insulating member for forming the outer circuit is exposed to the outside by removing selectively the metal plate except a metal bump forming portion. A cavity(30) is formed on the resultant structure and the inner circuit is selectively exposed to the outside by removing partially the insulating member.

Abstract translation: 通过使用底部封装的金属凸块和空腔延长顶部封装和底部封装之间的距离，提供了POP（封装上封装）基板及其制造方法以增加集成芯片的数量而不增加厚度。 内部电路（12）形成在核心基板（10）的表面上。 具有与外部电路（52）相对应的电路图案的金属板经由绝缘构件（40）形成在核心基板的表面上。 此时，电路图案与内部电路相反。 通过选择性地除去金属凸起形成部分以外的金属板，用于形成外部电路的绝缘部件的一部分暴露于外部。 在所得到的结构上形成空腔（30），并且通过部分地去除绝缘构件，内部电路选择性地暴露于外部。

公开(公告)号：KR100677184B1

公开(公告)日：2007-02-02

申请号：KR1020060012985

申请日：2006-02-10

Applicant: 삼성전기주식회사

Inventor： 정회구 ,  강명삼 ,  김지은 ,  박정현

IPC: H01L23/48 ,  H01L23/28

Abstract: A method for manufacturing a substrate is provided to reduce the thickness of the substrate by using a cavity capable of mounting an IC(Integrated Circuit). An inner circuit is formed at a core layer(S410). A protection agent is formed within a cavity forming region of the resultant structure(S420). An insulating layer and a copper thin film are sequentially deposited on the core layer. An outer circuit is formed on the resultant structure by etching selectively the copper thin film(S430). A cavity is formed by etching selectively the insulating layer(S450). The protection agent is removed therefrom(S460). A bonding pad is formed in the cavity(S470). A dry film is used as the protection agent.

Abstract translation: 提供一种用于制造基板的方法，以通过使用能够安装IC（集成电路）的空腔来减小基板的厚度。 内层电路形成在核心层（S410）。 保护剂形成在所得结构的空腔形成区域内（S420）。 绝缘层和铜薄膜依次沉积在芯层上。 通过选择性蚀刻铜薄膜在所得结构上形成外部电路（S430）。 通过选择性蚀刻绝缘层来形成空腔（S450）。 保护剂从中移除（S460）。 接合垫形成在空腔中（S470）。 使用干膜作为保护剂。