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1.发明专利
公开(公告)号：KR102231101B1
公开(公告)日：2021-03-23
申请号：KR1020140160570A
申请日：2014-11-18
Applicant: 삼성전기주식회사
CPC classification number: H05K3/007 , H05K1/187 , H01L2224/04105 , H01L2224/2518 , H01L2224/92144 , H05K2201/10015 , H05K3/42
Abstract: 본 발명은 소자 내장형 인쇄회로기판 및 그 제조방법에 관한 것이다.
보다 구체적으로, 본 발명의 일 실시 예에 따른 소자 내장형 인쇄회로기판은 절연층의 일면에 형성된 제1 회로층 및 타면에 형성된 제2 회로층을 포함하는 기판 및 전극부를 가지며, 상기 기판의 절연층에 매립된 소자를 포함하고, 상기 소자의 전극부는 제1 회로층과 접촉된다
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公开(公告)号：KR1020170089188A
公开(公告)日：2017-08-03
申请号：KR1020160009278
申请日：2016-01-26
Applicant: 삼성전기주식회사
Abstract: 본발명의일 실시형태는내부에코일부가배치된바디및 상기코일부와연결된외부전극을포함하며, 상기바디는자성입자를포함하며, 상기자성입자는제1 자성입자및 상기제1 자성입자보다입경이작은제2 자성입자를포함하고, 상기제1 자성입자는단축대비장축의비가 1.8 내지 5.3인코일전자부품을제공한다.
Abstract translation: 本发明的一个实施例包括具有设置在其中的内回波部分和连接到线圈部分的外电极的主体，其中主体包括磁性颗粒，磁性颗粒具有第一磁性颗粒和第二磁性颗粒 并且第一磁性颗粒具有1.8至5.3的短轴与长轴之比。
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公开(公告)号：KR1020170037331A
公开(公告)日：2017-04-04
申请号：KR1020150136782
申请日：2015-09-25
Applicant: 삼성전기주식회사
CPC classification number: H05K3/4697 , H05K1/185 , H05K3/0011 , H05K3/0035 , H05K3/4682 , H05K2201/09127 , H05K2201/09563 , H05K2201/10636 , H05K2203/1469 , Y02P70/611
Abstract: 본발명의실시예에따른인쇄회로기판은, 일면에제1 회로가내장된제1 절연층, 상기제1 절연층타면에적층된제2 절연층, 상기제2 절연층에형성되는캐비티, 상기캐비티내에접착부재로실장되는전자소자및 상기전자소자가내장되도록상기제2 절연층상에적층되는제3 절연층을포함한다.
Abstract translation: 根据本发明实施例的印刷电路板包括：第一绝缘层，在其一个表面上嵌入有第一电路;第二绝缘层，堆叠在第一绝缘层的另一个表面上;空腔，形成在第二绝缘层中， 一种电子装置，其用粘合构件安装在空腔中，以及第三绝缘层，其层压在第二绝缘层上，使得电子装置被嵌入。
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公开(公告)号：KR1020160043357A
公开(公告)日：2016-04-21
申请号：KR1020140137636
申请日：2014-10-13
Applicant: 삼성전기주식회사
CPC classification number: H05K1/183 , H05K1/185 , H05K3/0097 , H05K3/305 , H05K3/306 , H05K3/4682 , H05K3/4697 , H05K2201/10015 , H05K2201/10636 , H05K2203/1536 , Y02P70/611
Abstract: 본발명은임베디드기판및 임베디드기판의제조방법에관한것이다. 본발명의실시예에따르면임베디드기판은절연층, 절연층내부에내장된소자, 절연층하면에매립되도록형성된제1 회로패턴, 절연층하면으로부터돌출되도록형성된제2 회로패턴및 소자와제2 회로패턴에접합되도록형성된비아를포함한다.
Abstract translation: 本发明涉及嵌入式基板和嵌入式基板的制造方法。 根据本发明的实施例，嵌入式基板包括：绝缘层; 嵌入绝缘层中的器件; 第一电路图案，被配置为嵌入在所述绝缘层的底表面中; 第二电路图案，被配置为从绝缘层的底表面突出; 以及经配置以结合到所述装置和所述第二电路图案的通孔。 本发明的目的是为嵌入式基板提供改进的信号传输可靠性。
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公开(公告)号：KR1020160010960A
公开(公告)日：2016-01-29
申请号：KR1020140091766
申请日：2014-07-21
Applicant: 삼성전기주식회사
CPC classification number: H05K1/113 , H01L21/4857 , H01L23/49811 , H01L23/49822 , H01L2924/0002 , H05K3/205 , H05K3/4007 , H05K3/4682 , H05K2201/0367 , H05K2201/09563 , H01L2924/00
Abstract: 본발명은절연층의일면으로상면이노출되도록상기절연층내에매립된제 1 회로패턴; 상기제 1 회로패턴의하면과접하도록상기절연층내에매립된결합패드; 및상기절연층의일면상에돌출되도록상기제 1 회로패턴의상면상에형성된범프패드;를포함하는인쇄회로기판에관한것이다.
Abstract translation: 本发明涉及具有嵌入式图案结构的印刷电路板及其制造方法，其中电路图案被稳定地嵌入，并且改进了与安装部件等的连接性。 印刷电路板包括：嵌入绝缘层中的第一电路图案，使得其上表面暴露于绝缘层的一个表面; 嵌入所述绝缘层中以与所述第一电路图案的下表面接触的耦合焊盘; 以及形成在所述第一电路图案的上表面上以在所述绝缘层的一个表面上突出的凸块焊盘。
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Patent Agency Ranking
公开(公告)号：KR101367953B1
公开(公告)日：2014-02-26
申请号：KR1020120151080
申请日：2012-12-21
Applicant: 삼성전기주식회사
IPC: H02M3/155
Abstract: The present invention relates to a boost converter. According to the the present invention, the boost converter comprises a transformer, a first switching unit, a clamp unit, and a stabilization unit. The transformer comprises a first coil and a second coil. The first coil receives input power. The second coil is connected to the first coil through electromagnetic coupling and has a predetermined coil ratio. The first switching unit switches on/off the input power transferred to the first coil according to predetermined duty. The clamp unit clamps voltage applied to an output diode with the difference between the input power and output voltage in a state of switching on the first switching unit. The stabilization unit comprises a second switch which operates switching complementarily to the on/off operation of the first switching unit and stabilizes the output power. The first switching unit comprises a first switch connected between the ground and the other end of the first coil. The clamp unit further comprises a first diode and a second diode. The first diode comprises an anode connected to one end of the first coil and a cathode connected to the other end of the second coil. The second diode comprises an anode connected to one end of an input power unit and a cathode connected to the other end of the second coil.
Abstract translation: 本发明涉及升压转换器。 根据本发明，升压转换器包括变压器，第一开关单元，夹紧单元和稳定单元。 变压器包括第一线圈和第二线圈。 第一个线圈接收输入电源。 第二线圈通过电磁耦合连接到第一线圈并具有预定的线圈比。 第一开关单元根据预定义务接通/断开传送到第一线圈的输入电力。 在接通第一开关单元的状态下，钳位单元将施加到输出二极管的电压钳位在输入功率与输出电压之间的差。 稳定单元包括第二开关，其与第一开关单元的接通/断开操作互补地进行操作，并稳定输出功率。 第一开关单元包括连接在第一线圈的接地端和另一端之间的第一开关。 钳位单元还包括第一二极管和第二二极管。 第一二极管包括连接到第一线圈的一端的阳极和连接到第二线圈的另一端的阴极。 第二二极管包括连接到输入功率单元的一端的阳极和连接到第二线圈的另一端的阴极。
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公开(公告)号：KR101089985B1
公开(公告)日：2011-12-05
申请号：KR1020100092565
申请日：2010-09-20
Applicant: 삼성전기주식회사
IPC: H03K19/0185
CPC classification number: H03K19/018521 , H03K19/0016 , H03K19/00353
Abstract: PURPOSE: A level shift circuit is provided to be normally operated regardless of a square wave voltage, a direct current voltage, and the duty of a control voltage for a RF(Radio Frequency) system. CONSTITUTION: A switching circuit(100) is connected between a preset gate node and an input terminal which receives an input voltage. A charging channel part(200) is connected to the switching circuit in parallel. The charging channel part offers the input voltage for charging. A charge circuit(300) is connected between the gate node and a controlling part which receives a control voltage. The charge circuit offers a gate voltage by charging a voltage through the charging channel part. A discharge path part(400) is connected to the charge circuit in parallel. The discharge path part offers a discharge path for the voltage which is charged in the charge circuit. An output transistor(500) performs a switching operation using a voltage difference between the input voltage of the input terminal and the charging voltage of the charge circuit.
Abstract translation: 目的：无论方波电压，直流电压以及射频（射频）系统的控制电压的占空比如何，电平移位电路均可正常工作。 构成：开关电路（100）连接在预置的栅极节点和接收输入电压的输入端子之间。 充电通道部分（200）并联连接到开关电路。 充电通道部分提供充电的输入电压。 充电电路（300）连接在栅极节点和接收控制电压的控制部分之间。 充电电路通过对充电通道部分的电压进行充电来提供栅极电压。 放电路径部分（400）并联连接到充电电路。 放电路径部分为充电电路中充电的电压提供放电路径。 输出晶体管（500）使用输入端子的输入电压与充电电路的充电电压之间的电压差进行开关动作。
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公开(公告)号：KR1020110045959A
公开(公告)日：2011-05-04
申请号：KR1020090102733
申请日：2009-10-28
Applicant: 삼성전기주식회사
IPC: H01L21/60
CPC classification number: H01L21/76885 , H01L21/02112 , H01L23/13 , H01L23/3128 , H01L24/48 , H01L24/97 , H01L2224/451 , H01L2224/48091 , H01L2224/4824 , H01L2224/48465 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/12042 , H01L2924/15311 , H01L2224/85 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
Abstract: PURPOSE: A ball grid array board, semiconductor chip package, and manufacturing method thereof are provided to manufacture two ball grid array substrates by a one-time process, thereby reducing the number of manufacturing processes. CONSTITUTION: An insulating layer(110) comprises a first side(111), a second side(112), and an opening(113). A semiconductor chip is mounted on the first side. The second side faces the first side. The opening connects the first side with the second side. A circuit pattern(120) is buried under the second side of the insulating layer. The circuit pattern includes a wire bonding pad(121) and a ball pad(122). A solder resist layer is formed on the circuit pattern.
Abstract translation: 目的：提供一种球栅阵列板，半导体芯片封装及其制造方法，通过一次性工艺制造两个球栅阵列基板，从而减少制造工艺的数量。 构成：绝缘层（110）包括第一侧（111），第二侧（112）和开口（113）。 半导体芯片安装在第一侧。 第二面朝向第一面。 开口连接第一面和第二面。 电路图案（120）被埋在绝缘层的第二侧下方。 电路图案包括导线焊盘（121）和球垫（122）。 在电路图案上形成阻焊层。
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公开(公告)号：KR1020110003097A
公开(公告)日：2011-01-11
申请号：KR1020090060702
申请日：2009-07-03
Applicant: 삼성전기주식회사
IPC: H05K3/40
Abstract: PURPOSE: A manufacturing method is provided to simultaneously form a via on two printed circuit board which have a buried circuit layer by using an adhesive plate. CONSTITUTION: A first base substrate and a second base substrate include an insulating layer(10) and a circuit layer(11,13) which is buried in both sides of the insulating layer. The first base substrate and the second base substrate are attached to both sides of an adhesive plate(30). A via, which passes through the insulating layer, is formed on the first base substrate and the second base substrate. The first base substrate and the second base substrate are separated from the adhesive plate. A via forming step comprises a step of processing a via hole, a step of forming a seed layer on the upper part of the insulating layer, a step of laminating a coating resist, a step of forming the via, and a step of removing an exposed seed layer.
Abstract translation: 目的：提供一种制造方法以在通过使用粘合板的埋置电路层的两个印刷电路板上同时形成通孔。 构成：第一基底基板和第二基底基板包括绝缘层（10）和埋在绝缘层两侧的电路层（11,13）。 第一基底基板和第二基底基板附着到粘合板（30）的两侧。 通过绝缘层的通孔形成在第一基底基板和第二基底基板上。 第一基底基板和第二基底基板与粘合板分离。 通孔形成步骤包括处理通孔的步骤，在绝缘层的上部形成种子层的步骤，层压涂膜抗蚀剂的步骤，形成通孔的步骤，以及除去 暴露种子层。
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公开(公告)号：KR100960954B1
公开(公告)日：2010-06-03
申请号：KR1020080071153
申请日：2008-07-22
Applicant: 삼성전기주식회사
CPC classification number: B32B38/04 , B32B38/10 , B32B2038/0092 , B32B2038/047 , B32B2309/105 , B32B2310/0843 , B32B2457/08 , H05K3/0035 , H05K3/108 , H05K3/421 , H05K3/428 , H05K3/4652 , H05K2201/0376 , H05K2203/0384 , H05K2203/0554 , Y10T156/1056 , Y10T156/1057 , Y10T156/1064 , Y10T156/1082
Abstract: 인쇄회로기판 제조방법이 개시된다. 층간 접속을 위한 비아를 포함하는 인쇄회로기판을 제조하는 방법으로서, 캐리어의 일면에 회로패턴을 형성하는 단계; 캐리어의 일면에, 비아에 상응하는 홈을 가공하는 단계; 캐리어의 일면을 절연체의 일면에 압착하는 단계; 캐리어를 제거하는 단계; 홈의 위치에 상응하여 절연체에 비아홀을 가공하는 단계; 및 비아홀의 내부에 도전성 물질을 형성하는 단계를 포함하는 인쇄회로기판 제조방법은, 비아를 형성하기 위한 홀 가공을 수월하게 수행할 수 있으며, 높은 설계자유도를 가질 수 있다.
인쇄회로기판, 캐리어, 비아, 홈
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