公开(公告)号：KR1020080035826A

公开(公告)日：2008-04-24

申请号：KR1020060102369

申请日：2006-10-20

Applicant: 삼성전자주식회사

Inventor： 고정덕 ,  황인석

IPC: H01L27/115

CPC classification number: H01L21/28273 ,  H01L21/28141 ,  H01L21/31144 ,  H01L21/76224

Abstract: A semiconductor device and a method for forming the same are provided to control pitting of a semiconductor substrate and program disturb of the semiconductor device by using first spacers and second spacers. A conductive pattern(104) is formed on an active region of a substrate(100). First spacers(114) including a conductive material are formed on a sidewall of an upper portion of the conductive pattern. Second spacers(118) including an insulating material are formed on lower portions of the first spacers. An isolation pattern(116) is formed to define the active region. When the isolation pattern is formed, preliminary isolation patterns protruded more than the surface of the substrate are formed. The conductive pattern has an upper surface higher than a surface of the preliminary isolation pattern. The preliminary isolation pattern is etched by using the conductive pattern and the first spacers as etch masks to form the isolation pattern having the upper surface which is same as the surface of the substrate.

Abstract translation: 提供一种半导体器件及其形成方法，用于通过使用第一间隔物和第二间隔物来控制半导体衬底的点蚀和半导体器件的编程干扰。 导电图案（104）形成在衬底（100）的有源区上。 包括导电材料的第一间隔物（114）形成在导电图案的上部的侧壁上。 包括绝缘材料的第二间隔物（118）形成在第一间隔物的下部。 形成隔离图案（116）以限定有源区域。 当形成隔离图案时，形成比衬底表面突出的预先隔离图案。 导电图案的上表面高于初步隔离图案的表面。 通过使用导电图案和第一间隔物作为蚀刻掩模来蚀刻初步隔离图案，以形成具有与基板表面相同的上表面的隔离图案。

公开(公告)号：KR1020040017126A

公开(公告)日：2004-02-26

申请号：KR1020020049255

申请日：2002-08-20

Applicant: 삼성전자주식회사

Inventor： 고정덕 ,  김준 ,  남정림 ,  박기종 ,  민충기

IPC: H01L21/304

Abstract: PURPOSE: A polishing head of a CMP(Chemical Mechanical Polishing) apparatus is provided to reduce the frictional force against a polishing pad by improving the structure of a retainer ring. CONSTITUTION: A polishing head(100) of a CMP apparatus is provided with a housing(110) having an air path, a carrier(120) connected with the housing for supporting a wafer, a wafer chucking part(130) loaded at the carrier for holding the wafer using vacuum pressure, and a retainer ring(140) for flatly contacting a polishing pad and protecting the wafer. At this time, the retainer ring includes a plurality of grooves for flowing slurry onto the polishing pad. At the time, predetermined corner portions of the groove are roundly formed.

Abstract translation: 目的：提供CMP（化学机械抛光）装置的抛光头，通过改进保持环的结构来减少对抛光垫的摩擦力。 构造：CMP设备的抛光头（100）设置有具有空气通道的壳体（110），与壳体连接以支撑晶片的载体（120），装载在载体上的晶片夹持部件（130） 用于使用真空压力保持晶片;以及用于平坦地接触抛光垫并保护晶片的保持环（140）。 此时，保持环包括用于将浆料流动到抛光垫上的多个槽。 此时，槽的预定角部被圆形地形成。

公开(公告)号：KR1020090041154A

公开(公告)日：2009-04-28

申请号：KR1020070106720

申请日：2007-10-23

Applicant: 삼성전자주식회사

Inventor： 고정덕 ,  신영주 ,  황인석

IPC: H01L21/304

CPC classification number: H01L21/02057 ,  B08B1/04 ,  H01L21/67046 ,  H01L21/67051 ,  H01L21/68728 ,  H01L21/6875

Abstract: An apparatus and a method for cleaning a substrate are provided to remove a defect formed in a thin film with a protrusion shape and the foreign material attached to the substrate by performing the deposition on the thin film with a particle continuously. A spin head(200) supports a substrate. A first cleaning unit cleans the substrate located on the spin head by a polishing method. A second cleaning unit(500) cleans the substrate located on the spin head by spraying the process solution. The first cleaning unit includes a support bar(420) and a polishing pad(440) coupled to the support bar to surround the circumference of the support bar. A rotation member(460) rotates the support bar around an axis when a first cleaning unit performs a cleaning process.

Abstract translation: 提供了一种用于清洁基板的装置和方法，以通过连续地用颗粒沉积在薄膜上来除去形成在具有突起形状的薄膜中的缺陷和附着到基板上的异物。 旋转头（200）支撑基底。 第一清洁单元通过抛光方法清​​洁位于旋转头上的基底。 第二清洁单元（500）通过喷射处理溶液来清洁位于旋转头上的基底。 第一清洁单元包括支撑杆（420）和联接到支撑杆以围绕支撑杆的圆周的抛光垫（440）。 当第一清洁单元执行清洁处理时，旋转构件（460）使支撑杆绕轴线旋转。

公开(公告)号：KR1020020089998A

公开(公告)日：2002-11-30

申请号：KR1020010029112

申请日：2001-05-25

Applicant: 삼성전자주식회사

Inventor： 고정덕 ,  고용선 ,  황인석

IPC: H01L21/31

Abstract: PURPOSE: An interlayer dielectric formation method of a semiconductor device is provided to prevent a dishing generating at a low density region by two-step polishing using a silica based slurry and a ceria based slurry. CONSTITUTION: An interlayer dielectric is formed on the semiconductor substrate(100) having transistors, a high density region(101) having high pattern density and a low density region(102) having low pattern density. A capping layer is formed on the interlayer dielectric. A planarized interlayer dielectric(152) is formed by two-step polishing of the interlayer dielectric using the capping layer. That is, high topology portions of the interlayer dielectric and the capping layer are firstly polished by CMP(Chemical Mechanical Polishing) using a silica based slurry. Then, the exposed interlayer dielectric is selectively polished by CMP using a different polishing selectivity between the interlayer dielectric and the capping layer and using a ceria based slurry. A polysilicon layer or a SiON layer is used as the capping layer.

Abstract translation: 目的：提供半导体器件的层间电介质形成方法，以通过使用二氧化硅基浆料和二氧化铈基浆料的两步抛光来防止在低密度区域产生凹陷。 构成：在具有晶体管，具有高图案密度的高密度区域（101）和具有低图案密度的低密度区域（102）的半导体衬底（100）上形成层间电介质。 在层间电介质上形成覆盖层。 通过使用覆盖层对层间电介质进行两步抛光来形成平坦化的层间电介质（152）。 也就是说，层间电介质和封盖层的高拓扑部分首先通过使用二氧化硅基浆料的CMP（Chemical Mechanical Polishing）进行抛光。 然后，通过CMP使用在层间电介质和覆盖层之间的不同抛光选择性并使用二氧化铈基浆料来选择性地抛光暴露的层间电介质。 多晶硅层或SiON层用作覆盖层。