公开(公告)号：KR100361081B1

公开(公告)日：2002-11-18

申请号：KR1019990047489

申请日：1999-10-29

Applicant: 삼성전자주식회사

Inventor： 곽선우 ,  윤정훈 ,  구병수 ,  권수영

IPC: H01L27/108

CPC classification number: H01L28/84

Abstract: PH도핑후의세정작업으로인해야기되는공정불량발생을막을수 있도록하여커패시터의파손을방지하고공정단순화를이룰수 있도록반도체소자의커패시터제조방법이개시된다. 이를구현하기위하여본 발명에서는, 반도체기판상에, 상기기판의표면이소정부분노출되도록매몰접촉창이구비된층간절연막을형성하는단계와; 상기매몰접촉창을포함한상기층간절연막상의소정부분에하부전극을형성하는단계와; 제 1 세정공정을실시하는단계와; 상기하부전극의표면노출부에 HSG를성장시키는단계와; 제 2 세정공정을실시하는단계와; 상기 HSG 내에 PH를도핑하는단계; 및진공의깸없이상기결과물상에유전막을형성하는단계로이루어진반도체소자의커패시터제조방법이제공된다.

公开(公告)号：KR100253091B1

公开(公告)日：2000-04-15

申请号：KR1019970061934

申请日：1997-11-21

Applicant: 삼성전자주식회사

Inventor： 한현 ,  남기흠 ,  곽선우

IPC: H01L21/48 ,  H01L21/68

CPC classification number: H01L21/67259 ,  H01L21/67098 ,  H01L21/67754 ,  H01L21/67766 ,  Y10S414/135

Abstract: PURPOSE: An elevator apparatus for transferring a wafer boat is provided to allow an automatic control of a horizontal attitude of wafers in the boat. CONSTITUTION: The elevator apparatus automatically adjusts the inclination of the wafer boat(34) so that the wafers(10) in the boat(34) are horizontally maintained. The elevator apparatus includes the wafer boat(34), a base(35) on which the boat(34) is supported, an elevator(37) for loading or unloading the boat(34) into or from a processing chamber, a sensing unit(43) for detecting the inclination of the boat(34) relative to the horizontal, a horizontal control unit(36) which is interposed between the base(35) and the elevator(37) and is drivable to maintain the boat(34) in such a position that the wafers(10) in the boat(34) lie in horizontal planes, and a control unit(44) for receiving information from the sensing unit(43) and, based on the information, outputting a control signal to the horizontal control unit(36).

Abstract translation: 目的：提供一种用于传送晶片舟的电梯装置，以便能够自动控制船中的晶片的水平姿态。 构成：电梯装置自动调节晶片舟（34）的倾斜度，使船体（34）中的晶片（10）水平地保持。 电梯设备包括晶片舟（34），支撑舟（34）的基座（35），用于将船（34）装载或从处理室中卸载的升降机（37），感测单元 （43），其用于检测所述船（34）相对于所述水平面的倾斜;水平控制单元（36），其插入在所述基座（35）和所述电梯（37）之间并且可驱动以维持所述船（34） 在这样一个位置上，舟皿（34）中的晶片（10）位于水平面上，以及用于从感测单元（43）接收信息的控制单元（44），并且基于该信息，将控制信号输出到 水平控制单元（36）。

公开(公告)号：KR1020010069054A

公开(公告)日：2001-07-23

申请号：KR1020000001288

申请日：2000-01-12

Applicant: 삼성전자주식회사

Inventor： 윤정훈 ,  권수영 ,  구병수 ,  곽선우

IPC: H01L27/108

Abstract: PURPOSE: A manufacturing method of a capacitor of a semiconductor device is provided to be capable of preventing the distribution defect of a dielectric layer thickness generated when a PH3 doping process and a dielectric layer forming process are performed in same recipe within single process chamber. CONSTITUTION: At first, an interlayer dielectric with a buried contact window is formed on a semiconductor substrate to expose a portion of the substrate. Then, a lower electrode is formed on a predetermined portion of the interlayer dielectric including the buried contact window. Next, a cleaning process is performed. Then, HSG(hemispherical grains) are growed on the surface exposure portion of the lower electrode within a process chamber. PH3 impurities are doped into the HSG without breaking vacuum status within another process chamber, and then a dielectric layer having thickness of (1/6-1/4)T is formed. Next, a residual dielectric layer having thickness of (5/6-3/4)T is formed on the formed dielectric layer within a batch type furnace. Finally, an upper electrode is formed on the dielectric layer.

Abstract translation: 目的：提供一种半导体器件的电容器的制造方法，以能够防止在单一处理室内以相同配方执行PH3掺杂工艺和电介质层形成工艺时产生的介电层厚度的分布缺陷。 构成：首先，在半导体衬底上形成具有埋入窗口的层间电介质，以露出衬底的一部分。 然后，在包括掩埋接触窗的层间电介质的预定部分上形成下电极。 接下来，执行清洁处理。 然后，HSG（半球形颗粒）在处理室内的下电极的表面曝光部分上生长。 将PH3杂质掺杂到HSG中，而不会在另一个处理室内破坏真空状态，然后形成厚度为（1 / 6-1 / 4）T的介电层。 接下来，在间歇式炉内的形成的电介质层上形成厚度为（5 / 6-3 / 4）T的残留电介质层。 最后，在电介质层上形成上电极。

公开(公告)号：KR1020010046575A

公开(公告)日：2001-06-15

申请号：KR1019990050398

申请日：1999-11-13

Applicant: 삼성전자주식회사

Inventor： 구병수 ,  김기영 ,  조종형 ,  곽선우

IPC: H01L27/108

Abstract: PURPOSE: A method for fabricating a capacitor of a semiconductor memory device is provided to improve reliability of a storage electrode by preventing the storage electrode from being damaged during formation of hemispherical grains. CONSTITUTION: In the method, a buried contact hole is formed in the first interlayer dielectric layer(20) on a substrate(10) and then filled with a conductive layer(30) for a buried contact. Next, the second interlayer dielectric layer having a window exposing the conductive layer(30) is formed on the first interlayer dielectric layer(20). Thereafter, the cylindrical storage electrode is formed in the window of the second interlayer dielectric layer. In particular, the storage electrode is formed from several conductive layers having an intermediate layer(53) with relatively higher doping concentration. Therefore, when the hemispherical grains(57) are formed on a surface of the storage electrode, the storage electrode is not damaged due to the intermediate layer(53). After that, a dielectric layer(70) and a conductive layer(80) for a plate electrode are formed thereon.

Abstract translation: 目的：提供一种用于制造半导体存储器件的电容器的方法，以通过防止存储电极在形成半球形晶粒期间被损坏来提高存储电极的可靠性。 构成：在该方法中，在衬底（10）上的第一层间电介质层（20）中形成掩埋接触孔，然后填充用于埋入触点的导电层（30）。 接下来，在第一层间电介质层（20）上形成具有暴露导电层（30）的窗口的第二层间电介质层。 此后，在第二层间电介质层的窗口中形成圆柱形存储电极。 特别地，存储电极由具有相对较高掺杂浓度的中间层（53）的多个导电层形成。 因此，当半导体晶粒（57）形成在存储电极的表面上时，由于中间层（53），存储电极不会损坏。 之后，在其上形成电介质层（70）和用于板电极的导电层（80）。

公开(公告)号：KR1020020088561A

公开(公告)日：2002-11-29

申请号：KR1020010027300

申请日：2001-05-18

Applicant: 삼성전자주식회사

Inventor： 곽선우

IPC: H01L21/205

Abstract: PURPOSE: A CVD(Chemical Vapor Deposition) method for forming HSG(Hemispherical Shaped Grain) silicon layer is provided to optimize the growth of the HSG silicon layer by forming silicon seed before crystallization of amorphous silicon. CONSTITUTION: A semiconductor substrate is loaded in a chamber of a first temperature(101-102). After pumping(103) the semiconductor substrate, the temperature in the chamber is to be rising(104). If the temperature of the chamber is reached to a second temperature in which is higher than the first temperature, a reacting gas is injected into the chamber and a silicon seed is formed(105). If the temperature of the chamber is reached to a third temperature in which higher than the second temperature, the silicon seed is continuously formed(106). Then, an annealing step is carried out(107).

Abstract translation: 目的：提供用于形成HSG（半球形晶粒）硅层的CVD（化学气相沉积）方法，以通过在非晶硅结晶之前形成硅晶粒来优化HSG硅层的生长。 构成：将半导体衬底装载在第一温度的室（101-102）中。 在泵送（103）半导体衬底之后，室内的温度将上升（104）。 如果室的温度达到高于第一温度的第二温度，则将反应气体注入室中并形成硅晶种（105）。 如果室的温度达到高于第二温度的第三温度，则连续形成硅晶种（106）。 然后，进行退火工序（107）。

公开(公告)号：KR100269315B1

公开(公告)日：2000-11-01

申请号：KR1019970062439

申请日：1997-11-24

Applicant: 삼성전자주식회사

Inventor： 김경훈 ,  박영욱 ,  남갑진 ,  원석준 ,  윤덕수 ,  곽선우

IPC: H01L21/26

CPC classification number: C23C16/45561 ,  C23C16/45557 ,  C23C16/481 ,  H01L21/28556 ,  H01L21/314 ,  Y10S438/907

Abstract: PURPOSE: A method for manufacturing semiconductor devices is provided to increase the throughput per unit time by reducing a temperature stabilization time of a wafer when semiconductor devices are manufactured using a sheet type equipment. CONSTITUTION: A method for manufacturing semiconductor devices stabilizes a wafer loaded to a chamber and performs a given process for the stabilized wafer. In order to increase the throughput of wafers per unit time by reducing the time consumed in the process stabilization step, the chamber pressure in the process stabilization step is maintained to be higher that in the process implementation step for a given hour.

Abstract translation: 目的：提供一种制造半导体器件的方法，以通过在使用片式设备制造半导体器件时降低晶片的温度稳定时间来增加每单位时间的吞吐量。 构成：制造半导体器件的方法使加载到腔室中的晶片稳定，并为稳定的晶片执行给定的工艺。 为了通过减少在过程稳定步骤中消耗的时间来增加每单位时间的晶片的生产量，过程稳定步骤中的腔室压力被保持为高于给定时间的过程实施步骤。

公开(公告)号：KR1019990041785A

公开(公告)日：1999-06-15

申请号：KR1019970062439

申请日：1997-11-24

Applicant: 삼성전자주식회사

Inventor： 김경훈 ,  박영욱 ,  남갑진 ,  원석준 ,  윤덕수 ,  곽선우

IPC: H01L21/26

Abstract: 램프가열 방식의 매엽식 장비를 이용하는 반도체장치의 제조방법에 대해 개시되어 있다. 이 방법은, 웨이퍼를 챔버내로 로딩하는 단계와, 챔버의 압력과 웨이퍼의 온도를 공정압력 및 공정온도보다 높게 상승시키는 단계와, 챔버의 압력 및 웨이퍼의 온도를 공정압력 및 공정온도로 하강시키는 단계와, 웨이퍼를 이용하여 소정의 공정을 진행하는 단계, 및 챔버의 진공을 해제하고 챔버 및 가스 주입관에 잔류하는 가스를 정화시키는 단계를 구비하여 이루어진다.

公开(公告)号：KR100328597B1

公开(公告)日：2002-03-15

申请号：KR1019990042800

申请日：1999-10-05

Applicant: 삼성전자주식회사

Inventor： 안중일 ,  현경호 ,  구병수 ,  곽선우

IPC: H01L27/108

CPC classification number: H01L28/84 ,  H01L27/1085 ,  Y10S438/964

Abstract: HSG의표면농도극대화하고, 디램소자의커패시턴스특성과 B·V 특성을동시에개선할수 있도록한 반도체소자의커패시터제조방법이개시된다. 이를구현하기위하여본 발명에서는, 반도체기판상에, 상기기판의표면이소정부분노출되도록매몰접촉창이구비된층간절연막을형성하는단계와, 상기결과물전면에저농도 P형불순물이도핑된비정질폴리실리콘막을형성하는단계와, 하부전극형성부를한정하는마스크패턴을이용하여상기폴리실리콘막을선택식각하여, 상기접촉창을포함한상기층간절연막상의소정부분에걸쳐하부전극을형성하는단계와, 상기하부전극의표면노출부에 HSG를성장시키는단계및, '저온/고압' 조건하에서상기 HSG 내에 PH를도핑하는단계로이루어진반도체소자의커패시터제조방법이제공된다.

公开(公告)号：KR1020010068597A

公开(公告)日：2001-07-23

申请号：KR1020000000595

申请日：2000-01-07

Applicant: 삼성전자주식회사

Inventor： 윤정훈 ,  구병수 ,  권수영 ,  곽선우

IPC: H01L21/22

Abstract: PURPOSE: A diffuser for manufacturing a semiconductor is provided to be capable of shortening work period and enhancing productivity as well as remarkably reducing fabrication costs and being simplified in its structure by positioning a susceptor for loading/unloading a wafer in a process position to perform a diffusion process without lifting the susceptor. CONSTITUTION: Wafer is loaded and unloaded to/from a susceptor(32) positioned within a chamber(30). A door(34) opened/closed for loading/unloading the wafer(W) on the susceptor(32) are equipped on one side of the chamber(30). The susceptor(32) is positioned in a process position within the chamber(30), and the door(34) is positioned in a position corresponding to the susceptor(32).

Abstract translation: 目的：提供用于制造半导体的漫射器，其能够缩短工作周期并提高生产率，并且通过将用于将晶片装载/卸载的基座放置在处理位置来执行 扩散过程而不提升感受器。 构成：将晶片装载到/从位于室（30）内的基座（32））卸载。 在所述腔室（30）的一侧装备有用于装载/卸载所述基座（32）上的所述晶片（W）的门（34）。 基座（32）位于室（30）内的处理位置，门（34）位于对应于基座（32）的位置。

公开(公告)号：KR1020010039195A

公开(公告)日：2001-05-15

申请号：KR1019990047489

申请日：1999-10-29

Applicant: 삼성전자주식회사

Inventor： 곽선우 ,  윤정훈 ,  구병수 ,  권수영

IPC: H01L27/108

CPC classification number: H01L28/84

Abstract: PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to prevent a defect caused by a cleaning process after a PH3 doping process, by consecutively performing the PH3 doping process and a process for forming a dielectric layer in a single-wafer-type chamber without affecting a vacuum state. CONSTITUTION: An interlayer dielectric is formed on a semiconductor substrate. The interlayer dielectric has a buried contact to expose a predetermined portion of the substrate. A lower electrode is formed in a predetermined portion on the interlayer dielectric including the buried contact hole. The first cleaning process is carried out. A hemispherical grain(HSG) is grown on the exposed portion of the surface of the lower electrode. The second cleaning process is carried out. PH3 is doped into the HSG. A dielectric layer is formed on the resultant structure without affecting a vacuum state.

Abstract translation: 目的：提供一种用于制造半导体器件的电容器的方法，以通过连续执行PH3掺杂工艺和在单晶片形成中形成电介质层的工艺来防止在PH3掺杂工艺之后由清洁工​​艺引起的缺陷， 不影响真空状态。 构成：在半导体衬底上形成层间电介质。 层间电介质具有掩埋接触以暴露基板的预定部分。 在包括埋入接触孔的层间电介质的预定部分中形成下电极。 进行第一次清洗处理。 半球形晶粒（HSG）生长在下电极表面的暴露部分上。 进行第二次清洗处理。 PH3掺杂到HSG中。 在所得结构上形成介电层而不影响真空状态。