公开(公告)号：KR1020000060454A

公开(公告)日：2000-10-16

申请号：KR1019990008768

申请日：1999-03-16

Applicant: 삼성전자주식회사

Inventor： 권흥안 ,  김형동 ,  안중일 ,  김성기

IPC: H01L21/28

Abstract: PURPOSE: A method for doping a gate conductive layer of a semiconductor device is provided to uniformly distribute substituted phosphorous atoms in the gate conductive layer. CONSTITUTION: A method for doping a gate conductive layer of a semiconductor device comprises the steps of: intervening a gate insulating layer on a semiconductor substrate(100) to form a gate conductive layer composed of a polysilicon; injecting PH3 gas and O2 gas into the entire surface of the gate conductive layer to form P2O5 layer(130) on the gate conductive layer; performing a thermal process within a predetermined scope of temperature so that a phosphorous atom in the P2O5 layer and a silicon atom in the gate conductive layer are substituted; and eliminating the P2O5 layer.

Abstract translation: 目的：提供一种用于掺杂半导体器件的栅极导电层的方法，以在栅极导电层中均匀分布取代的磷原子。 构成：用于掺杂半导体器件的栅极导电层的方法包括以下步骤：在半导体衬底（100）上插入栅极绝缘层，以形成由多晶硅构成的栅极导电层; 在所述栅极导电层的整个表面注入PH 3气体和O 2气体，以在所述栅极导电层上形成P2O5层（130）; 在预定的温度范围内进行热处理，使得P2O5层中的磷原子和栅极导电层中的硅原子被取代; 并消除P2O5层。

公开(公告)号：KR101716473B1

公开(公告)日：2017-03-15

申请号：KR1020100129309

申请日：2010-12-16

Applicant: 삼성전자주식회사

Inventor： 김기철 ,  이종철 ,  권흥안 ,  이현욱

IPC: H01L21/02 ,  H01L21/66

Abstract: 다층유전막을포함하는반도체소자의제조방법을개시한다. 본발명에따른반도체소자의제조방법은반도체기판상에금속산화층을형성하는단계및 금속산화층상에금속원자및 실리콘원자를포함하는다층실리케이트층을형성하는단계를포함하되, 다층실리케이트층은, 포함된금속원자및 실리콘원자의개수합계중 실리콘원자의개수가가지는비율인실리콘농도가서로다른적어도 2개의금속실리케이트층들을포함한다.

Abstract translation: 目的：通过使用多层介质层作为电容器电介质或阻挡绝缘膜，将具有可靠性的易失性或非易失性存储器半导体器件提供给半导体器件的制造方法。 构成：在半导体衬底（100）上形成金属氧化物层（520）。 在金属氧化物层上形成第一多层硅酸盐层（540）和第二多层硅酸盐层（560）。 第一多层硅酸盐层具有第一硅氧烷浓度。 第二多层硅酸盐层具有第二硅氧烷浓度。 第一多层硅酸盐层和第二多层硅酸盐层分别包含铪 - 硅酸锆。 第一多层硅酸盐层的厚度比第二多层硅酸盐层的厚度厚。 第一多层硅酸盐层和第二多层硅酸盐层包含两个或更多个金属硅酸盐层。

公开(公告)号：KR1020120067748A

公开(公告)日：2012-06-26

申请号：KR1020100129309

申请日：2010-12-16

Applicant: 삼성전자주식회사

Inventor： 김기철 ,  이종철 ,  권흥안 ,  이현욱

IPC: H01L21/02 ,  H01L21/66

CPC classification number: H01L21/02142 ,  H01L21/02123 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02172 ,  H01L22/12

Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to a volatile or nonvolatile memory semiconductor device having reliability by using a multilayer dielectric layer as a capacitor dielectric or a blocking insulation film. CONSTITUTION: A metal-oxide layer(520) is formed on a semiconductor substrate(100). A first multilayer silicate layer(540) and a second multilayer silicate layer(560) are formed on the metal-oxide layer. The first multilayer silicate layer has first silicone concentration. The second multilayer silicate layer has second silicone concentration. The first multilayer silicate layer and the second multilayer silicate layer respectively comprise hafnium-zirconium silicate. The thickness of the first multilayer silicate layer is thicker than the thickness of the second multilayer silicate layer. The first multilayer silicate layer and the second multilayer silicate layer comprise two or more metal silicate layers.

Abstract translation: 目的：通过使用多层介质层作为电容器电介质或阻挡绝缘膜，将具有可靠性的易失性或非易失性存储器半导体器件提供给半导体器件的制造方法。 构成：在半导体衬底（100）上形成金属氧化物层（520）。 在金属氧化物层上形成第一多层硅酸盐层（540）和第二多层硅酸盐层（560）。 第一多层硅酸盐层具有第一硅氧烷浓度。 第二多层硅酸盐层具有第二硅氧烷浓度。 第一多层硅酸盐层和第二多层硅酸盐层分别包含铪 - 硅酸锆。 第一多层硅酸盐层的厚度比第二多层硅酸盐层的厚度厚。 第一多层硅酸盐层和第二多层硅酸盐层包含两个或更多个金属硅酸盐层。

公开(公告)号：KR1020020014217A

公开(公告)日：2002-02-25

申请号：KR1020000047386

申请日：2000-08-17

Applicant: 삼성전자주식회사

Inventor： 임정수 ,  문강욱 ,  손용운 ,  권흥안

IPC: H01L21/31

CPC classification number: C30B25/105 ,  C30B31/12

Abstract: PURPOSE: An apparatus for forming a thin film having a reflection unit is provided to prevent contamination particles from being dropped to a wafer, by forming the reflection unit on a susceptor such that the reflection unit reflects heat energy radiated from the susceptor to the wafer. CONSTITUTION: A wafer loading region(43) is formed on a wafer heating unit(40). A shower head(52) sprays source gas capable of reaching the surface of the wafer when the wafer is loaded to the wafer loading region, installed in a position facing the wafer loading region. The reflection unit(44) reflects the heat energy radiated from the wafer loading region to the wafer loading region, installed between the shower head and the wafer heating unit. A pumping unit(56) controls the inner pressure of a chamber(38) including the wafer heating unit, the shower head and the reflection unit, and exhausts reaction byproducts generated inside the chamber to the outside of the chamber.

Abstract translation: 目的：提供一种用于形成具有反射单元的薄膜的装置，以通过在基座上形成反射单元使得反射单元将从基座辐射的热能反射到晶片来防止污染颗粒落到晶片上。 构成：在晶片加热单元（40）上形成晶片加载区（43）。 当晶片装载到晶片装载区域时，喷头（52）喷射能够到达晶片表面的源气体，该晶片装载区域安装在面向晶片装载区域的位置。 反射单元（44）将从晶片加载区域辐射的热能反射到安装在淋浴喷头和晶片加热单元之间的晶片装载区域。 泵送单元（56）控制包括晶片加热单元，淋浴头和反射单元的腔室（38）的内部压力，并且将在室内产生的反应副产物排出到腔室的外部。

公开(公告)号：KR1020080020753A

公开(公告)日：2008-03-06

申请号：KR1020060083995

申请日：2006-09-01

Applicant: 삼성전자주식회사

Inventor： 강남욱 ,  권흥안 ,  한충근

IPC: H01L21/3065 ,  H01L21/02

CPC classification number: H01J37/32862

Abstract: A method for preventing contamination of a process gas injection nozzle is provided to prevent particles from being formed in a process gas supply nozzle by continuously flowing purge gas like N2 gas and NF3 gas toward a process gas supply nozzle while the supply of process gas through the process gas supply nozzle stops. A semiconductor substrate having a silicon oxide layer is introduced into a process chamber of etch equipment(S300). Process gas for removing the silicon oxide layer is injected into the process chamber through the process gas supply nozzle(S302). Purge gas is firstly flowed through the process gas supply nozzle(S304). While the purge gas reacts with the silicon oxide layer to form reaction products, purge gas is secondly flowed through the process gas supply nozzle(S306). While the semiconductor substrate is heated, purge gas is thirdly flowed through the process gas supply nozzle(S308). The first, second and third flow processes for flowing the purge gas through the process gas supply nozzle can be performed continuously.

Abstract translation: 提供一种防止工艺气体注入喷嘴的污染的方法，以防止在工艺气体供给喷嘴中通过连续地将吹扫气体像N 2气体和NF 3气体一样流向工艺气体供给喷嘴，同时通过 工艺气体供应喷嘴停止。 将具有氧化硅层的半导体衬底引入蚀刻设备的处理室（S300）。 用于除去氧化硅层的工艺气体通过工艺气体供给喷嘴注入工艺室（S302）。 吹扫气体首先流过工艺气体供应喷嘴（S304）。 当吹扫气体与氧化硅层反应形成反应产物时，吹扫气体二次流过工艺气体供应喷嘴（S306）。 当半导体衬底被加热时，净化气体第三次流过工艺气体供应喷嘴（S308）。 用于使净化气体流过工艺气体供应喷嘴的第一，第二和第三流动过程可以连续进行。

公开(公告)号：KR1020040081976A

公开(公告)日：2004-09-23

申请号：KR1020030016599

申请日：2003-03-17

Applicant: 삼성전자주식회사

Inventor： 권흥안

IPC: H01L27/108

Abstract: PURPOSE: A method for forming a capacitor dielectric film is provided to prevent crack of an interlayer dielectric and contamination of a chamber by restraining abnormal oxidation of a tungsten silicide layer. CONSTITUTION: A semiconductor substrate is loaded in a chamber. The temperature in the chamber rises to oxidation temperature under nitrogen atmosphere(A). Nitrogen supply is stopped and thermal oxidation processing is carried out(B). Oxygen in the chamber is exhausted. Then, the temperature in the chamber is falling under nitrogen atmosphere(C). The oxidation temperature is 800°C and over.

Abstract translation: 目的：提供形成电容器电介质膜的方法，以通过抑制硅化钨层的异常氧化来防止层间电介质的裂纹和室的污染。 构成：将半导体衬底装入腔室。 室内温度升高到氮气氛下的氧化温度（A）。 停止氮气供应并进行热氧化处理（B）。 室中的氧气已耗尽。 然后，室内的温度在氮气氛下（C）下降。 氧化温度为800℃以上。

公开(公告)号：KR1020040108031A

公开(公告)日：2004-12-23

申请号：KR1020030038769

申请日：2003-06-16

Applicant: 삼성전자주식회사

Inventor： 고경석 ,  권흥안 ,  구자억

IPC: H01L21/205

Abstract: PURPOSE: A vertical diffusion furnace for manufacturing semiconductor is provided to deposit uniformly a thin film on each wafer by infiltrating deeply a process gas into every corner of a boat with a plurality of wafers using an enhanced inner tube with protrusions. CONSTITUTION: A vertical diffusion furnace(100) includes an outer tube, an inner tube, and a boat. The outer tube(200) is connected with a gas inlet line(110) and a gas exhaust line(120). The inner tube(300) with an opening at its upper portion is located in the outer tube. A boat(400) for loading a plurality of wafers(W) is located in the inner tube. A plurality of protrusions are formed on an inner wall of the inner tube. The diameter of an upper portion is smaller than that of a lower portion in the inner tube.

Abstract translation: 目的：提供用于制造半导体的垂直扩散炉，通过使用具有突起的增强内管将多个晶片将工艺气体深深渗透到具有多个晶片的船的每个角落中，以均匀地沉积在每个晶片上。 构成：垂直扩散炉（100）包括外管，内管和船。 外管（200）与气体入口管线（110）和排气管线（120）连接。 在其上部具有开口的内管（300）位于外管中。 用于装载多个晶片（W）的船（400）位于内管中。 在内管的内壁上形成有多个突起。 上部的直径小于内管中的下部的直径。

公开(公告)号：KR100375985B1

公开(公告)日：2003-03-15

申请号：KR1020000047386

申请日：2000-08-17

Applicant: 삼성전자주식회사

Inventor： 임정수 ,  문강욱 ,  손용운 ,  권흥안

IPC: H01L21/31

CPC classification number: C30B25/105 ,  C30B31/12

Abstract: A wafer treatment apparatus includes a wafer heating device having a wafer-load region at an upper portion, a shower head opposing the wafer-load region for ejecting/directing a source gas toward the wafer surface, and a reflecting apparatus positioned between the shower head and the heating device for reflecting thermal energy radiated from the heating device back toward the wafer-load region. The reflecting apparatus includes a reflector positioned above and opposing the wafer-load region, and a supporter for supporting the reflector. The reflector may have a flattened reflecting surface facing toward the wafer-load region, or may be a semi-spherical type reflector having a concave mirror facing toward the wafer-load region. The reflector can be controlled to move vertically relative to the wafer.

Abstract translation: 一种晶片处理装置包括晶片加热装置和反射装置，所述晶片加热装置在上部具有晶片加载区域，与晶片加载区域相对的用于将源气体向晶片表面喷射/引导的喷头，以及位于喷头 以及用于将从加热装置辐射的热能反射回晶片加载区域的加热装置。 反射装置包括位于晶片加载区上方并与其相对的反射器，以及用于支撑反射器的支撑件。 反射器可以具有面向晶片加载区域的平坦反射表面，或者可以是具有面向晶片加载区域的凹面镜子的半球形反射器。 可以控制反射器相对于晶片垂直移动。