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    반도체 장치 및 그 제조방법
    2.
    发明公开
    반도체 장치 및 그 제조방법 审中-实审
    半导体器件及其形成方法

    公开(公告)号：KR1020150049167A

    公开(公告)日：2015-05-08

    申请号：KR1020130129376

    申请日：2013-10-29

    Applicant: 삼성전자주식회사

    Inventor： 이의복 ,  백종민 ,  김도형 ,  마츠다츠카사 ,  조영우 ,  홍종서

    IPC: H01L21/28 ,  H01L21/31

    CPC classification number: H01L21/7682 ,  H01L21/02296 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/762 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/76849 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76885

    Abstract: 본발명은반도체장치및 그제조방법을제공한다. 본발명의반도체장치제조방법은장치기판상에개구부들을갖는층간절연막을형성하는것; 상기개구부들내에제공되며, 측부보다두꺼운바닥부를가지는금속막을형성하는것; 상기금속막을리플로우시켜, 상기개구부들내에금속패턴들을각각형성하는것; 및상기개구부들내에캐핑패턴들을형성하여, 상기금속패턴들을덮는것을포함하되, 상기금속패턴들의상면은상기층간절연막의최상면보다낮은레벨을가질수 있다.

    Abstract translation: 提供半导体器件及其制造方法。 制造半导体器件的方法包括以下步骤：在衬底上形成具有开口的层间绝缘膜; 形成设置在所述开口中并且具有比所述侧更厚的底部部分的金属膜; 回流金属膜并在开口中分别形成金属图案; 在开口中形成覆盖图案并覆盖金属图案，其中金属图案的上表面可以具有比层间绝缘膜的最上表面更低的水平。

    반도체 소자의 제조 방법
    3.
    发明公开
    반도체 소자의 제조 방법 无效
    制造半导体器件的方法

    公开(公告)号：KR1020140043949A

    公开(公告)日：2014-04-14

    申请号：KR1020120104109

    申请日：2012-09-19

    Applicant: 삼성전자주식회사

    Inventor： 마츠다츠카사 ,  김진남 ,  윤종호 ,  이종명

    IPC: H01L21/288 ,  H01L21/28

    CPC classification number: H01L21/76883 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885

    Abstract: A method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes a step of forming a first conductive sacrificial layer on a substrate, a step of forming a second insulating sacrificial layer on the first sacrificial layer, a step of etching the first and the second sacrificial layer and forming an opening part to expose the upper surface of the substrate, a step of conformally forming a seed layer on the first and the second sacrificial layer which have the opening part, and a step of forming a conductive pattern which buries the opening part formed in the seed layer by plating.

    Abstract translation: 提供一种制造半导体器件的方法。 制造半导体器件的方法包括在衬底上形成第一导电牺牲层的步骤，在第一牺牲层上形成第二绝缘牺牲层的步骤，蚀刻第一和第二牺牲层并形成 开口部露出基板的上表面，在具有开口部的第一牺牲层和第二牺牲层上保形地形成种子层的工序，以及形成埋入种子形成的开口部的导电图案的工序 电镀层。

    듀얼 다마신 배선 구조체를 포함하는 반도체 소자
    6.
    发明公开
    듀얼 다마신 배선 구조체를 포함하는 반도체 소자 无效
    具有双重DAMASCENE金属化结构的半导体器件

    公开(公告)号：KR1020130056014A

    公开(公告)日：2013-05-29

    申请号：KR1020110121732

    申请日：2011-11-21

    Applicant: 삼성전자주식회사

    Inventor： 윤종호 ,  최길현 ,  마츠다츠카사 ,  정은지

    IPC: H01L21/28

    CPC classification number: H01L23/53238 ,  H01L21/76831 ,  H01L21/76846 ,  H01L21/76865 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53242 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PURPOSE: A semiconductor device including a dual damascene wiring structure is provided to implement a thin thickness by chemically combining a top seed layer with a top interlayer dielectric layer to form a top barrier layer. CONSTITUTION: A bottom conductive layer(170) is electrically connected to a device layer(120). A bottom barrier layer(160) is located on the sidewall and the bottom of the bottom conductive layer. A top conductive layer(190) is located on the bottom conductive layer. A top barrier layer(180) is located on the sidewall and the bottom of the top conductive layer. The top barrier layer includes a material which is different from the material of the bottom barrier layer.

    Abstract translation: 目的：提供一种包括双镶嵌布线结构的半导体器件，以通过化学组合顶部种子层与顶部层间电介质层来实现薄的厚度以形成顶部阻挡层。 构成：底部导电层（170）电连接到器件层（120）。 底部阻挡层（160）位于底部导电层的侧壁和底部。 顶部导电层（190）位于底部导电层上。 顶部阻挡层（180）位于顶部导电层的侧壁和底部。 顶部阻挡层包括与底部阻挡层的材料不同的材料。

    반도체 장치의 형성 방법
    7.
    发明公开
    반도체 장치의 형성 방법 有权
    形成半导体器件的方法

    公开(公告)号：KR1020100099575A

    公开(公告)日：2010-09-13

    申请号：KR1020090018132

    申请日：2009-03-03

    Applicant: 삼성전자주식회사

    Inventor： 마츠다츠카사 ,  최길현 ,  이종명

    IPC: H01L21/28

    CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/3105 ,  H01L21/32051 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PURPOSE: A method for forming a semiconductor device is provided to obtain the superior quality by preventing the metal diffusion of a metal pattern into the concave part of the semiconductor device. CONSTITUTION: An interlayer insulating film(114) with a concave part(116) is formed in a semiconductor substrate(110). A plasma treatment is performed with respect to the inner side of the concave part. A barrier metal film is formed on the plasma treated inner side of the concave part. A seed layer is formed on the surface of the barrier metal film. A metal bulk layer is formed on the seed layer.

    Abstract translation: 目的：提供一种用于形成半导体器件的方法，以通过防止金属图案进入半导体器件的凹部的金属扩散来获得优异的质量。 构成：在半导体衬底（110）中形成具有凹部（116）的层间绝缘膜（114）。 相对于凹部的内侧进行等离子体处理。 在凹部的等离子体处理内侧上形成阻挡金属膜。 在阻挡金属膜的表面上形成种子层。 在种子层上形成金属体层。

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