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公开(公告)号：KR1020170011076A
公开(公告)日：2017-02-02
申请号：KR1020150103023
申请日：2015-07-21
IPC: C09D11/30 , C09D11/38 , C09D11/322 , C09D11/326
Abstract: 잉크젯프린터에적용가능한잉크조성물이개시된다. 본잉크조성물은, 안료, 습윤제, 용매, 폴리비닐알코올수지및 계면활성제를포함하며, 습윤제는, 프로필렌글리콜, 글리세린, 부틸렌글리콜, 트리에틸렌글리콜, 글루코오스, 프룩토스, 옥수수시럽및 소르비톨중 적어도하나를포함한다.
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公开(公告)号：KR1020100064467A
公开(公告)日：2010-06-15
申请号：KR1020080122913
申请日：2008-12-05
Applicant: 삼성전자주식회사
Abstract: PURPOSE: A complex programmable logic device code download method in a dual processor and a method thereof are provided to store a CPLD binary in a S/W binary data area in the dual processor, thereby automatically updating a CPLD code by CPLD binary update. CONSTITUTION: A host processor extracts a CPLD code from a CPLD(Complex Programmable Logic Device) binary in a S/W binary data area(307). A slave processor temporarily stores the CPLD code(311). The slave processor generates a JTAG(Joint Test Action Group) signal(315). The slave processor temporarily stores a CPLD code of the CPLD(321). The slave processor calculates a checksum value(325). The host processor displays a CPLD download complete message(329).
Abstract translation: 目的：提供双处理器中的复杂可编程逻辑器件代码下载方法及其方法，以将CPLD二进制存储在双处理器中的S / W二进制数据区域中，从而通过CPLD二进制更新自动更新CPLD代码。 构成：主机处理器从S / W二进制数据区域（307）中的CPLD（复杂可编程逻辑器件）二进制文件中提取CPLD代码。 副处理器临时存储CPLD代码（311）。 从属处理器产生一个JTAG（联合测试动作组）信号（315）。 从处理器临时存储CPLD的CPLD代码（321）。 从属处理器计算校验和值（325）。 主机处理器显示CPLD下载完成消息（329）。
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公开(公告)号：KR1020090007978A
公开(公告)日：2009-01-21
申请号：KR1020070071239
申请日：2007-07-16
Applicant: 삼성전자주식회사
CPC classification number: H01L2224/48257
Abstract: A semiconductor device and a formation method thereof are provided to form a share contact plug of a dumbbell shape, thereby reducing damage of a spacer disposed in a side of a gate electrode in a share contact hole forming process. A gate insulating layer(120) and a gate electrode(130) are formed on a semiconductor substrate(100). A spacer(140) is formed in a side wall of the gate electrode. An interlayer insulating film(150) is formed on the front of the semiconductor substrate. A shared contact hole including a first part(180a) exposing the gate electrode by pattering the interlayer insulating film, a second part(180b) exposing the semiconductor substrate and a third part(180c) connecting the first part and the second part is formed. The first part, the second part and the third part are arranged along a first direction. The first and second parts respectively have maximum widths in a second direction orthogonal to the first direction. The third part has a width smaller than the maximum widths of the first and second parts in the second direction.
Abstract translation: 提供半导体器件及其形成方法以形成哑铃形状的共用接触塞，从而减少在共用接触孔形成过程中设置在栅电极侧的间隔件的损坏。 在半导体衬底（100）上形成栅极绝缘层（120）和栅电极（130）。 在栅电极的侧壁上形成间隔物（140）。 在半导体衬底的前面形成有层间绝缘膜（150）。 形成共通接触孔，其包括通过图案化层间绝缘膜暴露栅电极的第一部分（180a），暴露半导体衬底的第二部分（180b）和连接第一部分和第二部分的第三部分（180c）。 第一部分，第二部分和第三部分沿着第一方向布置。 第一和第二部分分别在与第一方向正交的第二方向上具有最大宽度。 第三部分的宽度小于第一和第二部分在第二方向上的最大宽度。
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公开(公告)号：KR1020150049167A
公开(公告)日：2015-05-08
申请号：KR1020130129376
申请日：2013-10-29
Applicant: 삼성전자주식회사
CPC classification number: H01L21/7682 , H01L21/02296 , H01L21/3105 , H01L21/31111 , H01L21/31116 , H01L21/762 , H01L21/764 , H01L21/76802 , H01L21/76849 , H01L21/76882 , H01L21/76883 , H01L21/76885
Abstract: 본발명은반도체장치및 그제조방법을제공한다. 본발명의반도체장치제조방법은장치기판상에개구부들을갖는층간절연막을형성하는것; 상기개구부들내에제공되며, 측부보다두꺼운바닥부를가지는금속막을형성하는것; 상기금속막을리플로우시켜, 상기개구부들내에금속패턴들을각각형성하는것; 및상기개구부들내에캐핑패턴들을형성하여, 상기금속패턴들을덮는것을포함하되, 상기금속패턴들의상면은상기층간절연막의최상면보다낮은레벨을가질수 있다.
Abstract translation: 提供半导体器件及其制造方法。 制造半导体器件的方法包括以下步骤：在衬底上形成具有开口的层间绝缘膜; 形成设置在所述开口中并且具有比所述侧更厚的底部部分的金属膜; 回流金属膜并在开口中分别形成金属图案; 在开口中形成覆盖图案并覆盖金属图案，其中金属图案的上表面可以具有比层间绝缘膜的最上表面更低的水平。
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公开(公告)号：KR100843073B1
公开(公告)日：2008-07-03
申请号：KR1020050072397
申请日：2005-08-08
Applicant: 삼성전자주식회사
Inventor： 조영우
IPC: H04L12/825 , H04L1/00
CPC classification number: H04L1/0009 , H04L47/10 , H04L47/263 , Y02D50/10
Abstract: 오류 정정 패킷을 이용한 전송률 제어 방법 및 이를 이용한 통신 장치가 제공된다.
본 발명의 실시예에 따른 오류 정정 패킷을 이용한 전송률 제어 방법은 데이터 패킷과 오류 정정 패킷이 소정의 비율로 구성된 제 1 패킷 그룹을 수신 장치에게 전송하는 단계, 상기 제 1 패킷 그룹에 관한 피드백 정보에 따라서 오류 정정 패킷의 비율이 조절된 제 2 패킷 그룹을 전송하는 단계, 및 상기 제 2 패킷 그룹에 관한 피드백 정보에 따라서 전송률을 조절하는 단계를 포함 한다.
전송률 제어, 오류 정정 패킷, 실시간 데이터-
Patent Agency Ranking
公开(公告)号：KR1020170070924A
公开(公告)日：2017-06-23
申请号：KR1020150178376
申请日：2015-12-14
Applicant: 삼성전자주식회사
IPC: H01L21/768 , H01L21/762 , H01L29/772 , H01L29/66
CPC classification number: H01L23/53295 , H01L23/5222 , H01L23/53238 , H01L23/53266
Abstract: 본발명은반도체소자및 이의제조방법에관한것으로, 보다상세하게는기판상의제1 절연막을포함하는층간절연막; 및상기제1 절연막내에배치된복수개의배선들을포함한다. 상기층간절연막은, 제1 영역및 에어갭이배치된제2 영역을갖고, 상기에어갭은, 상기제2 영역내의한 쌍의상기배선들사이에정의되며, 상기제1 영역의상기제1 절연막의상면은, 상기제1 영역내의적어도하나의상기배선들의상면보다더 낮다.
Abstract translation: 本发明涉及一种半导体器件及其制造方法，并且更具体地涉及一种半导体器件，该半导体器件包括：在衬底上的包括第一绝缘膜的层间绝缘膜; 以及布置在第一绝缘膜中的多个布线。 其中，层间绝缘膜具有第一区域和第二区域，在该第一区域和第二区域中设置有气隙，并且气隙限定在第二区域中的一对互连之间， 轮廓表面低于第一区域中的至少一个配线的上表面。
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7.发明授权압축률 향상을 위해 개선된 컨텍스트 모델 선택을 사용하는ＣＡＢＡＣ 부호화 방법 및 장치, 그리고 ＣＡＢＡＣ복호화 방법 및 장치 有权압축률향된된C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C및
公开(公告)号：KR100750165B1
公开(公告)日：2007-08-17
申请号：KR1020060017239
申请日：2006-02-22
Applicant: 삼성전자주식회사
Inventor： 조영우
IPC: H04N19/13
Abstract: A method and an apparatus for CABAC(Context-based Adaptive Binary Arithmetic Coding) encoding, a method and an apparatus for CABAC decoding, and a computer-readable recording medium storing programs for performing the methods are provided to restore original input data without an ambiguity occurrence by previously performing test decoding during an encoding process so as to prevent the occurrence of the ambiguity. The first context model based on statistics of previously input symbols and the second context model having a different MPS(Most Probable Symbol) value from the first context model are selected(S110). If a value of a current input symbol is equal to the MPS value of the first context model, or the second context model is not selected, the current input symbol is encoded using the first context model(S140). If the value of the current input symbol is different from the MPS value of the first context model, or the second context model is selected, the current input symbol is encoded using the second context model(S130).
Abstract translation: 提供了一种用于CABAC（基于上下文的自适应二进制算术编码）编码的方法和设备，用于CABAC解码的方法和设备，以及存储用于执行这些方法的程序的计算机可读记录介质，以恢复原始输入数据而没有歧义 通过在编码处理期间先前执行测试解码来防止出现模糊，从而防止出现歧义。 选择基于先前输入符号的统计量的第一上下文模型和具有来自第一上下文模型的不同MPS（最可能符号）值的第二上下文模型（S110）。 如果当前输入符号的值等于第一上下文模型的MPS值，或者未选择第二上下文模型，则使用第一上下文模型编码当前输入符号（S140）。 如果当前输入符号的值不同于第一上下文模型的MPS值，或者第二上下文模型被选择，则使用第二上下文模型编码当前输入符号（S130）。
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公开(公告)号：KR100735526B1
公开(公告)日：2007-07-04
申请号：KR1020060012279
申请日：2006-02-08
Applicant: 삼성전자주식회사
IPC: H01L21/027
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公开(公告)号：KR100632467B1
公开(公告)日：2006-10-09
申请号：KR1020050074448
申请日：2005-08-12
Applicant: 삼성전자주식회사
IPC: H01L21/3205
Abstract: A semiconductor memory device and its manufacturing method are provided to prevent short of an upper wire and a lower wire and to increase electrical characteristics of the semiconductor memory device. Lower wires(22) are formed on a semiconductor substrate(10) in one direction. An interlayer dielectric(24) is formed on the semiconductor substrate where the lower wires are formed. The interlayer dielectric is selectively etched to form a via hole(26) exposing the lower wires. A trench(28) is located in the interlayer dielectric by being arranged vertically with respect to the lower wires. The trench is projected from the lower wires toward one side. A lower portion of the projected region is connected to the via hole. The conductive layer for gap-filling the via hole and the trench is formed and planarized to form an upper damascene wire(46) within the interlayer dielectric.
Abstract translation: 提供一种半导体存储器件及其制造方法，以防止上导线和下导线短路并增加半导体存储器件的电特性。 下导线（22）沿一个方向形成在半导体衬底（10）上。 在形成下导线的半导体衬底上形成层间电介质（24）。 选择性蚀刻层间电介质以形成暴露下部导线的通孔（26）。 沟槽（28）通过相对于下部导线垂直布置而位于层间电介质中。 沟槽从下部导线向一侧突出。 投影区域的下部连接到通孔。 用于间隙填充通孔和沟槽的导电层被形成并被平面化以在层间电介质内形成上大马士革线（46）。
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