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公开(公告)号：KR1020170108765A
公开(公告)日：2017-09-27
申请号：KR1020160103671
申请日：2016-08-16
Applicant: 삼성전자주식회사
CPC classification number: H01L27/0886 , H01L21/823437 , H01L21/823475 , H01L23/528 , H01L27/0207 , H01L27/088
Abstract: 반도체장치및 그제조방법이제공된다. 상기반도체장치는제1 액티브영역, 상기제1 액티브영역과이격된제2 액티브영역, 및제1 가상의라인을따라상기제1 액티브영역과교차되는제1 게이트파트와, 제2 가상의라인을따라상기제2 액티브영역과교차되는제2 게이트파트와, 상기제1 게이트파트와상기제2 게이트파트를연결하고, 상기제1 가상의라인및 상기제2 가상의라인과교차되는제3 가상의라인을따라연장되는제3 게이트파트를포함하는제1 게이트라인을포함하되, 상기제1 내지제3 게이트파트는, 동일평면상에배치된다.
Abstract translation: 提供了一种半导体器件及其制造方法。 的半导体器件是在第一有源区，所述第一有源区和从所述第二有源区域，第一栅极部分和沿着mitje第一虚拟交叉线与所述第一有源区中的第二假想线间隔 所述第二和第二栅极部分相交的有源区域，第一栅极部分和栅极部分的第二连接，该第一假想线和第三虚拟的线相交的第二虚拟线 并且第一栅极线包括沿着第一栅极线延伸的第三栅极部分，其中第一至第三栅极部分布置在同一平面上。
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公开(公告)号：KR1020020051154A
公开(公告)日：2002-06-28
申请号：KR1020000080700
申请日：2000-12-22
Applicant: 삼성전자주식회사
Inventor： 박윤문
IPC: H01L21/283
Abstract: PURPOSE: A formation method of a self-alignment contact plug of semiconductor devices is provided to solve an etching stopped problem according to an increase of a polymer production by forming contact plugs self-aligned through gate electrodes regardless of considering an etching selectivity between an interlayer dielectric and a nitride spacer. CONSTITUTION: A number of gate electrodes(20) are formed on a semiconductor substrate(10). At this time, the upper surfaces and both sidewalls of the gate electrodes(20) are respectively enclosed with insulating layers made of nitride capping layers(32) and nitride spacers(34). Conductive pattern(50) self-aligned by the gate electrodes(20) are formed on the regions between the gate electrodes(20).
Abstract translation: 目的：提供半导体器件的自对准接触插塞的形成方法，以通过形成通过栅极电极自对准的接触插塞，而不考虑中间层之间的蚀刻选择性，根据聚合物生产的增加来解决蚀刻停止的问题 电介质和氮化物间隔物。 构成：在半导体衬底（10）上形成多个栅电极（20）。 此时，栅电极（20）的上表面和两个侧壁分别被由氮化物覆盖层（32）和氮化物间隔物（34）制成的绝缘层封闭。 在栅电极（20）之间的区域上形成由栅电极（20）自对准的导电图案（50）。
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公开(公告)号：KR1020160094239A
公开(公告)日：2016-08-09
申请号：KR1020150029837
申请日：2015-03-03
Applicant: 삼성전자주식회사
CPC classification number: H01L27/0207 , H01L27/0886 , H01L29/66545 , H01L29/6681 , H01L29/7831
Abstract: 안정적인더미패턴을포함하는반도체장치및 그제조방법을제공하는것이다. 상기반도체장치는제1 폭을갖는제1 더미게이트; 상기제1 더미게이트와길이방향으로인접하고, 제2 폭을갖는제2 더미게이트; 및상기제1 더미게이트와상기제2 더미게이트를연결하는적어도하나의브리지를포함하고, 상기제1 폭과상기제2 폭은공정최소선폭보다좁다.
Abstract translation: 提供一种包括稳定虚拟图案的半导体器件及其制造方法。 半导体器件包括：具有第一宽度的第一伪栅极; 第二伪栅极，其具有在纵向方向上与第一伪栅极相邻的第二宽度; 以及连接第一和第二伪栅极的至少一个桥，其中第一宽度和第二宽度的宽度比最小处理线的宽度窄。
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公开(公告)号：KR1020110064661A
公开(公告)日：2011-06-15
申请号：KR1020090121349
申请日：2009-12-08
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L21/32139 , H01L21/0337 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529 , Y10S438/947 , G03F7/0035 , G03F7/70466 , G03F7/70475
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to simultaneously form conductive patterns with different widths, thereby keeping the intervals between conductive patterns with different widths. CONSTITUTION: First patterns which are separated each other and a second pattern are formed. A second sub mask is formed while first sub masks are formed. First mask patterns(25a,25b,25c,25d,25e,25f) are formed and a second mask pattern is formed. The first patterns, the second pattern, the first sub masks, and the second sub mask are eliminated. First conductive patterns and a second conductive pattern are formed by etching the conductive films of the first mask patterns and the second mask pattern.
Abstract translation: 目的：提供一种用于制造半导体器件的方法，以同时形成具有不同宽度的导电图案，从而保持具有不同宽度的导电图案之间的间隔。 构成：形成彼此分离的第一图案和第二图案。 在形成第一子掩模时形成第二子掩模。 形成第一掩模图案（25a，25b，25c，25d，25e，25f）并形成第二掩模图案。 消除了第一图案，第二图案，第一子掩模和第二子掩模。 通过蚀刻第一掩模图案和第二掩模图案的导电膜来形成第一导电图案和第二导电图案。
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公开(公告)号：KR1020110055180A
公开(公告)日：2011-05-25
申请号：KR1020090112098
申请日：2009-11-19
Applicant: 삼성전자주식회사
IPC: H01L27/10
CPC classification number: H01L27/3223 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L27/11519 , H01L27/11529 , H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A semiconductor device and a forming method thereof are provided to implement high integration by including core contacts with the same width and pitch as cell contacts. CONSTITUTION: Active regions(ACT) are formed in a cell region and a core region. An interlayer insulation layer covers the active regions. The cell contacts pass through the interlayer insulation layer and are electrically connected to the active region of the cell region in a first direction. Core contacts(CoC) pass through the interlayer insulation layer and are arranged on the active region of the core region in the first direction. The core contacts includes an upper connection core contact and a dummy contact(DmC). The upper connection core contact is electrically connected to the active regions. The dummy contact is insulated from the active region in one side of the upper connection contact.
Abstract translation: 目的：提供半导体器件及其形成方法以通过包括具有与电池触点相同的宽度和间距的芯触点来实现高集成度。 构成：活性区域（ACT）形成在细胞区域和核心区域中。 层间绝缘层覆盖活性区域。 电池触点通过层间绝缘层，并且在第一方向上电连接到电池区的有源区。 芯触点（CoC）通过层间绝缘层，并且沿着第一方向布置在芯区域的有源区域上。 芯触点包括上连接芯触点和虚拟触点（DmC）。 上连接芯触点电连接到有源区。 虚拟触点与上连接触点一侧的有源区绝缘。
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Patent Agency Ranking
公开(公告)号：KR101462606B1
公开(公告)日：2014-11-19
申请号：KR1020080098780
申请日：2008-10-08
Applicant: 삼성전자주식회사
CPC classification number: G11C16/0483 , H01L27/11521 , H01L27/11524
Abstract: 본 발명은 공통 비트 라인을 가지는 비휘발성 메모리 소자를 제공한다. 본 발명에 따른 비휘발성 메모리 소자는 제1 선택 트랜지스터; 제1 선택 트랜지스터와 직렬로 연결되고 제1 선택 트랜지스터에 비하여 낮은 구동 전압을 가지는 제2 선택 트랜지스터; 제1 선택 트랜지스터 및 복수의 제2 선택 트랜지스터들을 각각 포함하는 제1 메모리 스트링; 제1 선택 트랜지스터 및 복수의 제2 선택 트랜지스터들을 각각 포함하는 제2 메모리 스트링; 제1 메모리 스트링의 제1 선택 트랜지스터 또는 제2 선택 트랜지스터들 중 하나와 연결되는 제1 스트링 선택 라인; 제2 메모리 스트링의 제1 선택 트랜지스터 또는 제2 선택 트랜지스터들 중 하나와 연결되는 제2 스트링 선택 라인; 및 제1 메모리 스트링 및 제2 메모리 스트링의 일단을 공통으로 연결하는 공통 비트 라인;을 포함한다.
비휘발성 메모리, 공통 비트 라인, 선택 트랜지스터, 구동 전압-
公开(公告)号：KR1020110029404A
公开(公告)日：2011-03-23
申请号：KR1020090087064
申请日：2009-09-15
Applicant: 삼성전자주식회사
IPC: H01L27/04
CPC classification number: H01L27/11531 , H01L27/11526 , H01L28/20 , H01L28/24
Abstract: PURPOSE: A semiconductor device with a resistor and a forming method thereof are provided to form a resistance pattern using process steps which manufacture a flash memory device, thereby forming the resistance pattern while minimizing addition of process steps. CONSTITUTION: A mold pattern defines a trench on a semiconductor substrate. A resistance pattern includes a body area and the first and second contact areas(CR1,CR2). The first and the second wires are connected to the first and second contact areas respectively. The first conductive pattern is arranged between the first wire and the first contact area. The second conductive pattern is arranged between the second wire and the second contact area.
Abstract translation: 目的：提供具有电阻器及其形成方法的半导体器件，以使用制造闪速存储器件的工艺步骤形成电阻图案，由此形成电阻图案同时最小化加工步骤。 构成：模具图案限定半导体衬底上的沟槽。 电阻图案包括主体区域和第一和第二接触区域（CR1，CR2）。 第一和第二导线分别连接到第一和第二接触区域。 第一导电图案布置在第一线和第一接触区之间。 第二导电图案布置在第二线和第二接触区之间。
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公开(公告)号：KR1020110017685A
公开(公告)日：2011-02-22
申请号：KR1020090075278
申请日：2009-08-14
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11521 , G11C16/0483 , H01L27/11519 , H01L21/31051 , H01L21/76224 , H01L27/11524
Abstract: PURPOSE: The semiconductor device and manufacturing method thereof easily control the threshold voltage of transistor. The semiconductor memory device which integrated and improves the reliability is offered. CONSTITUTION: The string structure comprises string selection transistors more than two serially connected to the first direction. The string selection line(SSL1, SSL2, SSL3) interlinks string selection transistors of string structures. The word line electrically interlinks memory transistors. The bit line(BL1, BL2) electrically interlinks string structures more than adjacent two.
Abstract translation: 目的：半导体器件及其制造方法容易控制晶体管的阈值电压。 提供集成并提高可靠性的半导体存储器件。 构成：串联结构包括串联连接到第一方向的两个串选择晶体管。 字符串选择行（SSL1，SSL2，SSL3）链接字符串结构的字符串选择晶体管。 字线电连接存储晶体管。 位线（BL1，BL2）比相邻的两个电连接串联结构。
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公开(公告)号：KR1020100039704A
公开(公告)日：2010-04-16
申请号：KR1020080098780
申请日：2008-10-08
Applicant: 삼성전자주식회사
CPC classification number: G11C16/0483 , H01L27/11521 , H01L27/11524
Abstract: PURPOSE: A non-volatile memory device with a common bit line is provided to increase the pitch between bit line contacts by sharing a single bit line through a single common bit line contact. CONSTITUTION: A second selection transistor(ST1_1A~ST1_8A) is serially connected to a first selection transistor and have low driving voltage compared to a first selection transistor. A first and a second memory string(MS1~MS8) respectively include the first selection transistor and the second selection transistors. The first string selection line is connected to one among the first selection transistor or the second selection transistors of the first memory string. The second string selection line is connected to one among the first selection transistor or the second selection transistors of the second memory string. A common bit line commonly interlinks one end of the first and the second memory string.
Abstract translation: 目的：提供具有公共位线的非易失性存储器件，以通过通过单个公共位线触点共享单个位线来增加位线触点之间的间距。 构成：与第一选择晶体管相比，第二选择晶体管（ST1_1A〜ST1_8A）串联连接到第一选择晶体管并具有低驱动电压。 第一和第二存储器串（MS1〜MS8）分别包括第一选择晶体管和第二选择晶体管。 第一串选择线连接到第一存储器串的第一选择晶体管或第二选择晶体管中的一个。 第二串选择线连接到第二存储器串的第一选择晶体管或第二选择晶体管中的一个。 公共位线通常将第一和第二存储器串的一端互连。
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公开(公告)号：KR101616972B1
公开(公告)日：2016-04-29
申请号：KR1020090087064
申请日：2009-09-15
Applicant: 삼성전자주식회사
IPC: H01L27/04
CPC classification number: H01L27/11531 , H01L27/11526 , H01L28/20 , H01L28/24
Abstract: 저항소자를갖는반도체장치및 그형성방법을제공한다. 이방법은반도체기판상에트렌치를정의하는주형패턴들을형성하고, 주형패턴들상에트렌치를가로지르는저항패턴을형성하고, 저항패턴상에서로이격된제 1 및제 2 도전패턴들을국소적으로형성하는단계를포함할수 있다.
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