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公开(公告)号：KR1020080065395A
公开(公告)日：2008-07-14
申请号：KR1020070002487
申请日：2007-01-09
Applicant: 삼성전자주식회사
Inventor： 신나래
IPC: H01L23/495
CPC classification number: H01L2224/73204
Abstract: A semiconductor chip package is provided to disperse the stress applied to inner leads by bending the inner leads of a semiconductor chip package. A semiconductor chip(32) is disposed on a base film(30). Inner leads(38) are disposed on the base film, electrically connected to the semiconductor chip and having a first bent portion. Outer leads(42) are positioned in substantially the same level as the inner leads, electrically connected to the inner leads. Pads can be disposed on the semiconductor chip, confronting the base film. Bumps(36) can be formed on the pads, connected to the inner leads.
Abstract translation: 提供半导体芯片封装以通过弯曲半导体芯片封装的内引线来分散施加到内引线的应力。 半导体芯片（32）设置在基膜（30）上。 内引线（38）设置在基膜上，与半导体芯片电连接并具有第一弯曲部分。 外引线（42）被定位成与内引线大致相同的电平，与内引线电连接。 衬垫可以布置在半导体芯片上，面对基膜。 可以在焊盘上形成凸起（36），连接到内引线。
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公开(公告)号：KR101900738B1
公开(公告)日：2018-09-20
申请号：KR1020120092056
申请日：2012-08-23
Applicant: 삼성전자주식회사
IPC: H01L23/12 , H01L21/60 , G02F1/1345
CPC classification number: H01L23/49838 , H01L23/4985 , H01L2924/0002 , H01L2924/00
Abstract: COF 기판은베이스필름, 제 1 상부도전패턴들, 적어도하나의제 2 상부도전패턴, 및하부도전패턴들을포함한다. 제 1 상부도전패턴들은상기베이스필름의상부면에배열된다. 제 1 상부도전패턴들각각은서로이격된인너패턴과아우터패턴을포함한다. 제 2 상부도전패턴은상기베이스필름의상부면에상기제 1 상부도전패턴들사이에위치하도록배열된다. 하부도전패턴들은베이스필름의하부면에배열되어, 상기인너패턴과상기아우터패턴을전기적으로연결시킨다. 따라서, 미세한피치를갖는패널패턴들간의쇼트발생이상기된 COF 기판구조에의해억제된다.
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公开(公告)号：KR1020080061602A
公开(公告)日：2008-07-03
申请号：KR1020060136523
申请日：2006-12-28
Applicant: 삼성전자주식회사
Inventor： 신나래
IPC: H01L21/60
CPC classification number: H01L2224/13099 , H01L2224/16 , H01L2224/17 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/00012
Abstract: A semiconductor chip for a TAP(tape automated bonding) package is provided to increase misalignment tolerance of a chip pad and a lead caused by deformation of a circuit board by using chip pads with mutually different widths. Inner chip pads(222,223) are disposed on a semiconductor substrate(210), one-dimensionally arranged on a first column parallel with a first side of the semiconductor substrate. Outermost chip pads(221) are disposed on the semiconductor substrate, one-dimensionally arranged on a second column between the first column and the first side. When seen from a vertical cross section parallel with the first side, the inner chip pads have a greater width than that of the outermost chip pads. When seen from a lateral view facing the first side, the outermost chip pads can be positioned between the inner chip pads.
Abstract translation: 提供了一种用于TAP（胶带自动接合）封装的半导体芯片，以通过使用具有相互不同宽度的芯片焊盘来增加由于电路板的变形引起的芯片焊盘和引线的不对准公差。 内部芯片焊盘（222,223）设置在半导体衬底（210）上，一维地布置在与半导体衬底的第一侧平行的第一列上。 最外面的芯片焊盘（221）设置在半导体衬底上，一维地布置在第一列和第一侧之间的第二列上。 当从与第一侧平行的垂直横截面看时，内部芯片焊盘的宽度大于最外面的芯片焊盘的宽度。 当从面向第一侧的横向视图看时，最外面的芯片焊盘可以位于内部芯片焊盘之间。
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Patent Agency Ranking
公开(公告)号：KR100744143B1
公开(公告)日：2007-08-01
申请号：KR1020060070887
申请日：2006-07-27
Applicant: 삼성전자주식회사
Abstract: A film wiring substrate, a semiconductor chip package using the same, and a flat panel display apparatus using the same are provided to increase an operational margin by increasing the capacitance between a power line and a grounding line. A flat display panel apparatus(100) using a film wiring substrate(120) includes a flat display panel(110) and a source drive PCB(Printed Circuit Board)(130). The source drive PCB(130) with a built-in power unit, a built-in memory unit, a built-in program unit, and a built-in buffer unit supplies a drive signal to the flat display panel(110). A semiconductor chip such as a source drive IC(Integrated Circuit)(140) is mounted on the film wiring substrate(120) to supply the drive signal from the source drive PCB(130) to the flat display panel(110). A plurality of signal lines(152) are connected between the source drive PCB(130) and the source drive IC(140) on the film wiring substrate(120).
Abstract translation: 提供了一种薄膜布线基板，使用该薄膜布线基板的半导体芯片封装以及使用该薄膜布线基板的平板显示装置，以通过增加电力线和接地线之间的电容来增加操作容限。 使用薄膜布线基板（120）的平面显示面板装置（100）包括平面显示面板（110）和源极驱动PCB（印刷电路板）（130）。 具有内置功率单元，内置存储单元，内置程序单元和内置缓冲单元的源驱动PCB（130）向平板显示面板（110）提供驱动信号。 诸如源驱动IC（集成电路）（140）的半导体芯片安装在膜布线衬底（120）上以将来自源驱动PCB（130）的驱动信号提供给平板显示面板（110）。 多条信号线（152）连接在薄膜布线基板（120）上的源极驱动PCB（130）和源极驱动IC（140）之间。
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公开(公告)号：KR1020140131813A
公开(公告)日：2014-11-14
申请号：KR1020130050907
申请日：2013-05-06
Applicant: 삼성전자주식회사
IPC: H01L23/498 , H01L23/48
CPC classification number: H01L23/49541 , H01L23/00 , H01L23/4824 , H01L23/49838 , H01L23/4985 , H01L24/16 , H01L2224/16225 , H05K1/118
Abstract: 본 발명은 분산 배치된 비아 플러그들을 포함하는 칩 온 필름 패키지에 관한 것이다. 필름 기판, 상기 필름 기판의 제1면 상에 배치되고 제1 길이를 갖는 제1 리드들 및 상기 제1 길이보다 긴 제2 길이를 갖는 제2 리드들, 상기 필름 기판을 관통하고, 상기 제1 리드들의 제1 단부들과 연결되는 제1 비아 플러그들 및 상기 제2 리드들의 제1 단부들과 연결되는 제2 비아 플러그들, 및 상기 필름 기판의 상기 제1면과 대향하는 제2면 상에 배치되고, 상기 제1 비아 플러그들과 연결되는 제1 단부들을 가진 제1 연결 리드들 및 상기 제2 비아 플러그들과 전기적으로 연결되는 제1 단부들을 가진 제2 연결 리드들을 포함할 수 있다.
Abstract translation: 本发明涉及一种包括分布式通孔插头的胶片封装。 薄膜封装上的芯片包括薄膜基片; 第一引线布置在薄膜基片的第一平面上并具有第一长度; 比第一引线长的第二引线; 首先穿过穿透薄膜基片并连接到第一引线的第一端的插头; 第二通孔，其连接到第二引线的第一端; 第一连接引线，其布置在面向第一平面的薄膜基板的第二平面上，并且具有连接到第一通孔塞的第一端; 以及具有电连接到第二通孔的第一端的第二连接引线。
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公开(公告)号：KR100771874B1
公开(公告)日：2007-11-01
申请号：KR1020060063506
申请日：2006-07-06
Applicant: 삼성전자주식회사
CPC classification number: H01L29/0657 , H01L23/3185 , H01L24/11 , H01L24/12 , H01L24/16 , H01L2224/1147 , H01L2224/13099 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10157
Abstract: A semiconductor bonding package and a manufacturing method thereof are provided to easily contact a circuit line with a bump of a semiconductor chip by forming the circuit line, while the semiconductor chip is inserted into a bare film substrate. A semiconductor bonding package includes a film substrate(200), a semiconductor chip, and a circuit line(220). A mount hole is formed on the film substrate. The semiconductor chip is inserted into the mount hole of the film substrate. A bump(125) is formed on a surface of the semiconductor chip. The circuit line is formed to be contacted with the bump on one surface of the film substrate and the semiconductor chip. An insulation film(110) is formed between the bumps.
Abstract translation: 提供半导体接合封装及其制造方法，通过形成电路线，将半导体芯片插入到裸膜基板中，容易地将电路线与半导体芯片的凸块接触。 半导体接合封装包括薄膜基板（200），半导体芯片和电路线（220）。 在薄膜基板上形成安装孔。 将半导体芯片插入到薄膜基板的安装孔中。 在半导体芯片的表面上形成凸块（125）。 电路线形成为与薄膜基板和半导体芯片的一个表面上的凸块接触。 在凸块之间形成绝缘膜（110）。
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公开(公告)号：KR1020150123058A
公开(公告)日：2015-11-03
申请号：KR1020140049462
申请日：2014-04-24
Applicant: 삼성전자주식회사
CPC classification number: H01L23/49838 , H01L23/49811 , H01L23/4985 , H01L23/564 , H01L2224/16225 , H05K1/189 , H05K2201/09781 , H05K2201/10128 , H05K2201/10681
Abstract: 본발명의기술적사상은테이프배선기판을이용하는반도체패키지에있어서, 더미칩 영역을포함하여폭이증가한반도체칩을적용하면서도테이프배선기판의사이즈증가를최소화할수 있는배선패턴을갖는테이프배선기판, 반도체패키지및 상기반도체패키지를포함한디스플레이장치를제공한다. 그반도체패키지는, 중앙부분에배치되고칩 배선들에연결된패드들이형성된유효칩 영역과, 상기유효칩 영역의측면에배치되고상기칩 배선들에연결되지않은패드들이형성된더미칩 영역을구비한반도체칩; 상기반도체칩이실장되는칩 실장부를구비하는베이스필름; 및상기베이스필름상에형성되고상기반도체칩의상기칩 배선들에전기적으로연결된다수의배선패턴들;을포함하고, 상기다수의배선패턴들중 일부인제1 배선패턴들은상기더미칩 영역하부의상기칩 실장부의제1 부분을통과한다.
Abstract translation: 本发明涉及使用带状布线基板的半导体封装，并且提供一种具有布线图案的带状布线基板，半导体封装以及包括该半导体封装的显示装置，该半导体封装包括虚设芯片区域，将半导体芯片与 增加宽度，并且由于其布线图案而使胶带布线基板的尺寸最小化。 半导体封装包括：半导体芯片，其包括设置在中心部分的有效芯片区域，并且设置有连接到芯片布线的焊盘，以及设置在有效芯片区域的侧面上的虚设芯片区域，并且设置有未连接到 芯片线; 基膜，其包括其上安装有半导体芯片的芯片安装单元; 以及多个图案，其形成在基底膜上并电连接到半导体芯片的芯片布线，其中作为线图案的一部分的第一线图案通过芯片安装单元的第一部分在下部 虚拟芯片面积。
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