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公开(公告)号：KR101446337B1
公开(公告)日：2014-10-02
申请号：KR1020080088473
申请日：2008-09-08
Applicant: 삼성전자주식회사
CPC classification number: G11C11/413
Abstract: 본 발명은 반도체 메모리 장치에 관한 것으로 복수의 워드라인들, 복수의 워드라인들과 교차하는 복수의 비트라인들, 복수의 워드라인들과 복수의 비트라인들이 교차되는 영역에 배치되는 복수의 메모리 셀들, 복수의 메모리 셀들의 동작을 제어하는 제어 신호에 따라 복수의 메모리 셀들에 제공되는 전원 전압을 제어하는 전압 제어부, 및 전압 제어부와 복수의 메모리 셀들 사이에 배치되어, 전원 전압을 소정의 레벨로 감소시키는 적어도 하나의 더미 셀을 포함한다.
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公开(公告)号：KR1020080054015A
公开(公告)日：2008-06-17
申请号：KR1020060126040
申请日：2006-12-12
Applicant: 삼성전자주식회사
Abstract: A display apparatus is provided to enhance the response speed of a liquid crystal by applying the pretilt on current image signals according to the comparison between a reference value and an image signal. A display apparatus includes plural pixels, a signal processing unit(610), and a data driver. The signal processing unit generates a preliminary signal based on previous and current image signals, compares the previous and current image signals and next image signals with a reference signal, and generates a compensation signal according to the reference signal and the preliminary signal based on the comparison result. The data driver converts the compensation signal into a data voltage and supplies the data voltage to the pixels.
Abstract translation: 提供一种显示装置，用于通过根据参考值和图像信号之间的比较对当前图像信号进行预倾斜来提高液晶的响应速度。 显示装置包括多个像素，信号处理单元（610）和数据驱动器。 信号处理单元基于先前的和当前的图像信号生成初步信号，并用参考信号对先前和当前图像信号和下一个图像信号进行比较，并根据参考信号和基于比较的初步信号产生补偿信号 结果。 数据驱动器将补偿信号转换成数据电压，并将数据电压提供给像素。
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公开(公告)号：KR1020080051598A
公开(公告)日：2008-06-11
申请号：KR1020060123031
申请日：2006-12-06
Applicant: 삼성전자주식회사
IPC: G02F1/133
CPC classification number: G02F1/133 , G09G3/3413 , G09G3/36 , G09G2320/0276
Abstract: A liquid crystal display apparatus is provided to prevent color break phenomenon by discriminating whether to perform the DCC of an image signal with gamma correction and improved response speed. A liquid crystal display apparatus includes a plurality of pixels, a gate driving part, a color correction part(610), a DCC(dynamic capacitance compensation) discriminating part(630), a DCC correction part(650), and a data driving part. The plurality of pixels has at least three colors. The gate driving part supplies a gate signal to the pixel. The color correction part generates a correction image signal of each color by compensating the image signal of at least three colors. The DCC discriminating part discriminates whether the compensated image signal is performed by using the DCC. The data driving part converts the output image signal to the data voltage to provide the pixels.
Abstract translation: 提供一种液晶显示装置，以通过鉴别是否执行具有伽马校正的图像信号的DCC和改进的响应速度来防止色差现象。 液晶显示装置包括多个像素，栅极驱动部分，颜色校正部分（610），DCC（动态电容补偿）识别部分（630），DCC校正部分（650）和数据驱动部分 。 多个像素具有至少三种颜色。 栅极驱动部分向像素提供栅极信号。 颜色校正部通过补偿至少三种颜色的图像信号来生成每种颜色的校正图像信号。 DCC识别部分通过使用DCC来辨别补偿的图像信号是否被执行。 数据驱动部分将输出图像信号转换为数据电压以提供像素。
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公开(公告)号：KR1020050064360A
公开(公告)日：2005-06-29
申请号：KR1020030095719
申请日：2003-12-23
Applicant: 삼성전자주식회사
IPC: H01L21/60
CPC classification number: H01L24/05 , H01L2224/05 , H01L2924/01029
Abstract: 프로브 팁에 의한 본딩패드의 손상을 방지하고, 칩 사이즈 증가없이도 안정된 본딩이 가능하도록 한 멀티 프로빙이 가능한 반도체 소자의 본딩패드 구조가 개시된다.
이를 위하여 본 발명에서는, 메탈 패드를 칩 내측으로 확장시켜, 원래의 메탈 패드 부분은 와이어 본딩이 진행되는 본딩영역으로 사용하고, 확장된 부분은 EDS 테스트가 진행되는 프로빙영역으로 사용토록 한 구조의 멀티 프로빙이 가능한 반도체 소자의 본딩패드 구조가 제공된다.
상기 구조로 본딩패드를 설계하면, EDS 테스트가 진행되는 부분과 와이어 본딩이 진행되는 부분이 분리되어 있어, 제품의 특성 평가를 위한 프로빙시 메탈 패드에 프로브 팁이 수차례 접촉되더라도 본딩영역쪽에는 프로브 팁에 의한 긁힘이 발생되지 않으므로, 칩 사이즈 증가없이도 와이어 본딩을 안정되게 실시할 수 있게 된다.-
公开(公告)号：KR100434189B1
公开(公告)日：2004-06-04
申请号：KR1020020015392
申请日：2002-03-21
Applicant: 삼성전자주식회사
IPC: H01L21/304
CPC classification number: B24B37/205 , B24B37/013 , B24B49/12 , B24D7/12 , G01B11/0625 , G01B11/0683
Abstract: In a chemical-mechanical polishing apparatus and a method for controlling the same, a table of an initial thickness of a layer to be polished concerning a detected light quantity of an endpoint detecting member is prepared in accordance with a polishing process recipe of the layer to be polished. The polishing process recipe of the layer is inputted, and a light quantity reflected from the layer is detected using the endpoint detecting member by projecting a light onto a semiconductor wafer. A thickness of the layer is calculated before the polishing process from a detection signal as the detected light quantity with reference to the table of the initial thickness of the layer concerning the detected light quantity. A polishing time is calculated from the calculated thickness before the polishing process to a desired thickness. An endpoint is detected by discounting the calculated polishing time while polishing the layer to be polished. Then, the polishing process is stopped when the endpoint is detected. An accurate control of a polishing endpoint can be achieved by simply adding a program to a controller of a CMP apparatus, and conditions and an efficiency of the operation can be improved.
Abstract translation: 在化学机械抛光设备及其控制方法中，根据层的抛光工艺配方制备与终点检测部件的检测光量有关的待抛光层的初始厚度的表格 被抛光。 输入该层的抛光工艺配方，并且通过将光投射到半导体晶片上，使用终点检测部件检测从该层反射的光量。 参照与检测光量有关的层的初始厚度表，根据作为检测光量的检测信号，在抛光处理之前计算该层的厚度。 从抛光处理之前的计算厚度到所需厚度计算抛光时间。 抛光待抛光层时，通过折算计算的抛光时间来检测终点。 然后，当检测到终点时停止抛光过程。 通过简单地将程序添加到CMP设备的控制器可以实现对抛光终点的精确控制，并且可以改善操作的条件和效率。
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Patent Agency Ranking
公开(公告)号：KR1020100029632A
公开(公告)日：2010-03-17
申请号：KR1020080088473
申请日：2008-09-08
Applicant: 삼성전자주식회사
CPC classification number: G11C11/413
Abstract: PURPOSE: A semiconductor memory device and an operation method thereof are provided to generate a voltage drop by including a dummy cell between a voltage control unit and a memory cell. CONSTITUTION: A voltage control unit(10) controls the voltage level of a power source provided to the memory cell according to the control signal indicating the operation of the memory cell array(20). The memory cell array comprises at least one dummy cell and a plurality of memory cells arranged in a cross section between a plurality of bit lines and a plurality of word lines. A row decoder activates a corresponding single word line by decoding a row address. A column decoder selects one corresponding bit line pair by decoding a column address. A sensing amplifying unit generates output signal by amplifying the difference between signals outputted from the column decoder.
Abstract translation: 目的：提供半导体存储器件及其操作方法，通过在电压控制单元和存储单元之间包括虚设单元来产生电压降。 构成：根据指示存储单元阵列（20）的动作的控制信号，电压控制单元（10）控制提供给存储单元的电源的电压电平。 存储单元阵列包括至少一个虚拟单元和布置在多个位线和多个字线之间的横截面中的多个存储单元。 行解码器通过解码行地址来激活对应的单字线。 列解码器通过解码列地址来选择一个对应的位线对。 感测放大单元通过放大从列解码器输出的信号之间的差来产生输出信号。
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公开(公告)号：KR1020080053563A
公开(公告)日：2008-06-16
申请号：KR1020060125269
申请日：2006-12-11
Applicant: 삼성전자주식회사
Abstract: A display apparatus is provided to monitor an operating state of various functions in a timing controller by implementing a watchdog routine in the timing controller. A display apparatus includes a timing controller(100), data and gate drivers, and a display panel(700). The timing controller outputs data and gate control signals in response to a main data signal and a main clock signal, which are inputted from the outside, and includes a watchdog routine that automatically recovers an erroneous operation by executing the reset. The data and gate drivers output data and gate signals in response to data and gate control signals, respectively. The display panel displays images by receiving the data and gate signals.
Abstract translation: 提供一种显示装置，通过在定时控制器中实现看门狗程序来监控定时控制器中的各种功能的操作状态。 显示装置包括定时控制器（100），数据和门驱动器以及显示面板（700）。 定时控制器响应于从外部输入的主数据信号和主时钟信号输出数据和门控制信号，并且包括通过执行复位自动恢复错误操作的看门狗程序。 数据和栅极驱动器分别响应于数据和门控信号输出数据和门信号。 显示面板通过接收数据和门信号来显示图像。
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公开(公告)号：KR1020070077670A
公开(公告)日：2007-07-27
申请号：KR1020060007378
申请日：2006-01-24
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76807 , H01L21/76829 , H01L21/76877
Abstract: A method for fabricating a semiconductor memory device and the semiconductor memory device fabricated by the same are provided to decrease resistance of via holes by increasing overlap margin between the via holes and a trench. A first interlayer dielectric(114), an etch stop layer and a second interlayer dielectric(118) are sequentially formed on a lower wiring(110), and then are partially etched to form via holes(132,134) exposing an upper surface of the lower wiring. A sacrificial layer(140) is formed to fill a portion of the via holes. The second interlayer dielectric formed on the via hole is etched to expand an upper portion of the via hole. After removing the sacrificial layer, a trench which is connected to the via hole is formed. An upper wiring is formed to fill the via holes and the trench.
Abstract translation: 提供一种用于制造半导体存储器件的方法和由其制造的半导体存储器件，以通过增加通孔和沟槽之间的重叠裕度来降低通孔的电阻。 第一层间电介质（114），蚀刻停止层和第二层间电介质（118）依次形成在下布线（110）上，然后被部分蚀刻以形成露出下部布线（110）的上表面的通孔（132,134） 接线。 形成牺牲层（140）以填充通孔的一部分。 在通孔上形成的第二层间电介质被蚀刻以扩大通孔的上部。 在去除牺牲层之后，形成连接到通孔的沟槽。 形成上部布线以填充通孔和沟槽。
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公开(公告)号：KR1020140049356A
公开(公告)日：2014-04-25
申请号：KR1020120115510
申请日：2012-10-17
Applicant: 삼성전자주식회사
IPC: H01L27/11 , H01L21/8244
CPC classification number: H01L27/1116 , H01L21/823892 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L27/1104
Abstract: The present invention provides a semiconductor device. The semiconductor device comprises a first well region, a second well region, and a third well region between the first and the second well regions. The first and the second well regions are first conductive types. The third well region is a second conductive type which is different from the first conductive type. A first active region is disposed in the first well region. A second active region is disposed in the second well region. A third active region is disposed closer to the second active region than to the first active region, in the third well region. A fourth active region is disposed closer to the first active region than to the second active region, in the third well region. A first conductive pattern crossing the first and the third active regions is disposed. A second conductive pattern crossing the second and the fourth active regions is disposed wherein the second conductive pattern is parallel with the first conductive pattern.
Abstract translation: 本发明提供一种半导体器件。 半导体器件包括在第一和第二阱区之间的第一阱区，第二阱区和第三阱区。 第一和第二阱区是第一导电类型。 第三阱区域是与第一导电类型不同的第二导电类型。 第一有源区设置在第一阱区中。 第二有源区域设置在第二阱区域中。 在第三阱区域中，第三有源区域比第一有源区域更靠近第二有源区域设置。 在第三阱区域中，第四有源区域比第二有源区域更靠近第一有源区域设置。 布置与第一和第三有源区交叉的第一导电图案。 布置与第二和第四有源区交叉的第二导电图案，其中第二导电图案与第一导电图案平行。
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公开(公告)号：KR1020120094822A
公开(公告)日：2012-08-27
申请号：KR1020110086505
申请日：2011-08-29
Applicant: 삼성전자주식회사
IPC: H01L27/11 , H01L21/8244 , H01L21/265
CPC classification number: H01L21/823412 , H01L21/76237 , H01L21/76895 , H01L21/823418 , H01L21/823475 , H01L27/1104 , H01L29/665 , H01L29/6659 , H01L29/7833
Abstract: PURPOSE: A semiconductor device and an optimized channel implant for manufacturing the same are provided to prevent n-p short due to a leakage of a contact area from the upper side to the lower side of a silicon trace. CONSTITUTION: A silicon trace(202) is doped with a first dopant. A plurality of polysilicon traces(204) are formed on the silicon trace and are separated from each other. A source/drain region(222) is formed in the silicon trace between two adjacent polysilicon traces and is doped with a second dopant. A channel region(220) is formed in the silicon trace. A part of the channel region near the source/channel region is doped with the second dopant.
Abstract translation: 目的：提供半导体器件和用于制造其的优化沟道植入物以防止由于硅迹线的上侧到下侧的接触区域的泄漏而导致n-p短路。 构成：硅迹线（202）掺杂有第一掺杂剂。 在硅迹线上形成多个多晶硅迹线（204）并且彼此分离。 源极/漏极区域（222）形成在两个相邻多晶硅迹线之间的硅迹线中，并且掺杂有第二掺杂剂。 在硅迹线中形成沟道区（220）。 在源极/沟道区附近的沟道区的一部分掺杂有第二掺杂剂。
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