公开(公告)号：KR1020090044810A

公开(公告)日：2009-05-07

申请号：KR1020070111067

申请日：2007-11-01

Applicant: 삼성전자주식회사

Inventor： 이용우 ,  이영미 ,  채민철 ,  김대중 ,  황재성

IPC: H01L21/027 ,  H01L21/265

CPC classification number: H01L21/3146 ,  H01L21/265 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/3185

Abstract: 본 발명은 고에너지 이온주입 시 이온주입 마스크 레이어의 종횡비(Aspect Ratio)를 증가시키는 이온주입 마스크 형성방법에 관한 것이다.
고에너지 이온주입 시 포토레지스트의 두께가 증가로 인한 종횡비 증가에 따른 패턴 러닝 및 리프팅이 발생됨을 방지하는 본 발명에 적용되는 이온주입 마스크 형성방법은, 반도체 기판 상에 필드영역을 형성하고 상기 반도체 기판 상에 비결정탄소막, 하드마스크막을 순차적으로 적층하는 단계와, 상기 하드마스크막 상에 식각 마스크 패턴을 형성하는 단계와, 상기 형성된 식각 마스크 패턴에 의해 상기 필드영역이 노출되도록 상기 하드마스막과 상기 비결정탄소막을 식각하여 상기 하드마스막과 상기 비결정탄소막의 패턴을 형성하는 단계를 포함한다.
필드영역의 고에너지 이온주입 시 하드마스크를 적용하여 종횡비 증가에 의한 패턴 리닝(Pattern leaning)현상과 포토레지스트의 리프팅현상의 발생을 방지한다.
플라즈마, 이온주입 마스크 형성, 종횡비 증가방지, 패턴리닝 현상방지, 포토레지스트 리프팅현상방지

公开(公告)号：KR1020090008667A

公开(公告)日：2009-01-22

申请号：KR1020070071789

申请日：2007-07-18

Applicant: 삼성전자주식회사

Inventor： 조우진 ,  이용우 ,  황재성 ,  권성운 ,  채민철

IPC: H01L27/11

CPC classification number: H01L27/0688 ,  H01L21/8221

Abstract: A semiconductor device and a method for manufacturing the same are provided to form the semiconductor device stably by redubbing the etching damage. A first transistor(110) is formed on a semiconductor substrate(100). An interlayer insulating film is formed on the semiconductor to cover the first transistor. A single crystal semiconductor plug(130) is formed inside the interlayer insulating film and is connected to the semiconductor substrate. A first recess region(124) is formed through the etching of the interlayer insulating film and the single-crystal semiconductor plug is exposed. A signal crystal semiconductor pattern(155) is formed on the first recess region and is connected to the single crystal semiconductor plug. A second transistor(170) is formed on the single-crystal semiconductor pattern.

Abstract translation: 提供半导体器件及其制造方法，以通过减少蚀刻损伤来稳定地形成半导体器件。 第一晶体管（110）形成在半导体衬底（100）上。 在半导体上形成层间绝缘膜以覆盖第一晶体管。 在层间绝缘膜的内部形成单晶半导体插头（130），与半导体基板连接。 通过蚀刻层间绝缘膜形成第一凹部区域（124），并露出单晶半导体插头。 信号晶体半导体图案（155）形成在第一凹部区域上并连接到单晶半导体插头。 在单晶半导体图案上形成第二晶体管（170）。

公开(公告)号：KR1020020091916A

公开(公告)日：2002-12-11

申请号：KR1020010030731

申请日：2001-06-01

Applicant: 삼성전자주식회사

Inventor： 채민철

IPC: H01L21/76

Abstract: PURPOSE: A method for forming an isolation layer of a semiconductor device is provided to improve gap-filling capability of the isolation layer by forming a trench structure having double slope using a polymer spacer. CONSTITUTION: A pad oxide layer(200) and a nitride layer(300) are formed on a silicon substrate(100) defined by an active region(101) and a field region(102). The silicon substrate(100) of the field region(102) is exposed by selectively etching the nitride layer(300) and the pad oxide layer(200) using a photoresist pattern as a mask. A polymer spacer is formed at both sidewalls of the resultant patterns. A trench is formed by firstly etching the exposed silicon substrate(100) using the polymer spacer as an etch stopper. After removing the polymer spacer and the photoresist pattern, a double-sloped trench structure(600) is formed by secondly etching the trench using the nitride layer(300) as an etch stopper.

Abstract translation: 目的：提供一种用于形成半导体器件的隔离层的方法，以通过使用聚合物间隔物形成具有双斜率的沟槽结构来改善隔离层的间隙填充能力。 构成：在由有源区域（101）和场区域（102）限定的硅衬底（100）上形成衬垫氧化物层（200）和氮化物层（300）。 通过使用光致抗蚀剂图案作为掩模选择性地蚀刻氮化物层（300）和焊盘氧化物层（200）来暴露场区（102）的硅衬底（100）。 在所得图案的两个侧壁处形成聚合物间隔物。 首先通过使用聚合物间隔物作为蚀刻停止剂蚀刻暴露的硅衬底（100）来形成沟槽。 在去除聚合物间隔物和光致抗蚀剂图案之后，通过使用氮化物层（300）作为蚀刻停止层，二次蚀刻沟槽来形成双斜面沟槽结构（600）。

公开(公告)号：KR1020080092182A

公开(公告)日：2008-10-15

申请号：KR1020070035728

申请日：2007-04-11

Applicant: 삼성전자주식회사

Inventor： 조우진 ,  황재성 ,  권성운 ,  채민철

IPC: H01L21/28

CPC classification number: H01L21/31111 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823437 ,  H01L21/823475

Abstract: A method for fabricating a semiconductor device is provided to prevent micro trenches and remove an oxide layer easily during an open process of a peripheral region having a high step by dry etching and removing a first oxide layer on a buffer layer and wet etching and removing a second oxide layer. A stack type semiconductor device includes a cell region(C) and a peripheral region(P). A method for fabricating the semiconductor device comprises the steps of: forming patterns(20) of the cell region including a gate structure; dry etching and removing a first oxide layer on a buffer layer(30); removing the buffer layer from the peripheral region; and wet etching and removing a second oxide layer which is formed under the buffer layer from the peripheral region. The buffer layer includes SiON. The buffer layer includes polysilicon and Si3N4.

Abstract translation: 提供了一种用于制造半导体器件的方法，以通过干法蚀刻和去除缓冲层上的第一氧化物层，并在湿蚀刻和去除 第二氧化物层。 堆叠型半导体器件包括单元区域（C）和周边区域（P）。 一种制造半导体器件的方法包括以下步骤：形成包括栅极结构的单元区域的图案（20）; 干蚀刻和去除缓冲层（30）上的第一氧化物层; 从周边区域去除缓冲层; 并从周边区域湿式蚀刻除去形成在缓冲层下面的第二氧化物层。 缓冲层包括SiON。 缓冲层包括多晶硅和Si 3 N 4。

公开(公告)号：KR1020080064033A

公开(公告)日：2008-07-08

申请号：KR1020070000742

申请日：2007-01-03

Applicant: 삼성전자주식회사

Inventor： 조우진 ,  하재규 ,  이용우 ,  황재성 ,  채민철

IPC: H01L21/8244 ,  H01L27/11

Abstract: A method for manufacturing a semiconductor device is provided to prevent pitting of an active region when patterning a poly silicon layer using a hard mask pattern. A method for manufacturing a semiconductor device includes: forming a conductive layer and a passivation layer(150) on a semiconductor substrate on which a plurality of active regions are defined by a device isolation region(110); forming a hard mask layer on the passivation layer; etching a partial region of the hard mask layer by using the passivation layer as an etch stop point to form a hard mask pattern; and patterning the passivation layer and the conductive layer using the hard mask pattern.

Abstract translation: 提供了一种用于制造半导体器件的方法，以在使用硬掩模图案来图案化多晶硅层时防止有源区的点蚀。 一种制造半导体器件的方法包括：在半导体衬底上形成导电层和钝化层（150），多个有源区域由器件隔离区域（110）限定在其上; 在钝化层上形成硬掩模层; 通过使用钝化层作为蚀刻停止点蚀刻硬掩模层的部分区域以形成硬掩模图案; 以及使用硬掩模图案来图案化钝化层和导电层。

公开(公告)号：KR1020080030199A

公开(公告)日：2008-04-04

申请号：KR1020060095961

申请日：2006-09-29

Applicant: 삼성전자주식회사

Inventor： 이종호 ,  손권 ,  박종석 ,  채민철 ,  김해주 ,  김광태 ,  최석진

IPC: H01L21/3065

CPC classification number: H01J37/32018 ,  H01J37/32642

Abstract: A plasma processing apparatus is provided to minimize the amount of byproducts including polymers deposited on a control ring by reducing thermal loss of the inside of the control ring. A process chamber performs a plasma process. An upper electrode and a lower electrode are arranged opposite to each other in the inside of the process chamber. A control ring(400) is formed to surround a plasma processing region between the upper electrode and the lower electrode in order to define plasma in the plasma processing region. The control ring includes an internal cavity buffering part(410) in order to minimize the heat of the inside of the plasma processing region to be transmitted through the control ring to the outside.

Abstract translation: 提供等离子体处理装置，通过减少控制环内部的热损失来最小化包括沉积在控制环上的聚合物的副产物的量。 处理室执行等离子体处理。 上部电极和下部电极在处理室的内部彼此相对布置。 形成控制环（400）以包围上电极和下电极之间的等离子体处理区域，以便限定等离子体处理区域中的等离子体。 控制环包括内部空腔缓冲部分（410），以便使待通过控制环传输到外部的等离子体处理区域的内部的热量最小化。

公开(公告)号：KR100739530B1

公开(公告)日：2007-07-13

申请号：KR1020060051035

申请日：2006-06-07

Applicant: 삼성전자주식회사

Inventor： 강윤승 ,  서준 ,  채민철 ,  황재성 ,  권성운 ,  조우진

IPC: H01L21/28 ,  H01L21/3205

Abstract: A method for manufacturing a semiconductor device is provided to form securely a contact hole with a large aspect ratio without the damage of an upper layer due to etching by patterning selectively the upper layer and a lower layer using etch selectivity of a multilayer mask structure. A lower pattern and an upper layer are sequentially formed on a semiconductor substrate(100). A lower mask layer(152) and an upper mask layer are sequentially formed on the upper layer. A hole for exposing an upper surface of the upper layer to the outside is formed on the resultant structure by patterning the upper and lower mask layers. An upper contact hole(145) for exposing an upper surface of the lower pattern to the outside is formed by performing a first anisotropic etching process on the upper layer using the upper mask pattern as an etch mask. A lower contact hole(135) prolonged from the upper contact hole is formed in the lower pattern by performing a second anisotropic etching process on the lower pattern using the lower mask pattern as an etch mask.

Abstract translation: 提供一种用于制造半导体器件的方法，以通过使用多层掩模结构的蚀刻选择性选择性地图案化上层和下层，从而可靠地形成具有大纵横比的接触孔，而不会由于蚀刻而损坏上层。 在半导体衬底（100）上依次形成下部图案和上部层。 下层掩模层（152）和上层掩模层依次形成在上层上。 通过对上和下掩模层构图，在所得结构上形成用于将上层的上表面暴露到外部的孔。 通过使用上掩模图案作为蚀刻掩模在上层上执行第一各向异性蚀刻工艺来形成用于将下图案的上表面暴露到外部的上接触孔（145）。 通过使用下掩模图案作为蚀刻掩模对下图案进行第二各向异性蚀刻工艺，在下图案中形成从上接触孔延长的下接触孔（135）。

公开(公告)号：KR101344019B1

公开(公告)日：2013-12-24

申请号：KR1020070111067

申请日：2007-11-01

Applicant: 삼성전자주식회사

Inventor： 이용우 ,  이영미 ,  채민철 ,  김대중 ,  황재성

IPC: H01L21/027 ,  H01L21/265

CPC classification number: H01L21/3146 ,  H01L21/265 ,  H01L21/3143 ,  H01L21/31608 ,  H01L21/3185

Abstract: 본발명의이온주입방법은, 반도체기판상에비결정탄소막을형성하고, 상기비결정탄소막상에하드마스크막을형성하고, 상기하드마스크막 상에포토레지스트패턴을형성하고, 상기포토레지스트패턴을제1 마스크로이용하여상기하드마스크막을식각하여상기비결정탄소막을노출시키고, 상기하드마스크막을제2 마스크로이용하여상기비결정탄소막을식각하여상기반도체기판을노출시키고, 및상기비결정탄소막을이온주입마스크로이용하여상기반도체기판내에이온을주입하는것을포함한다.

公开(公告)号：KR1020090010586A

公开(公告)日：2009-01-30

申请号：KR1020070073825

申请日：2007-07-24

Applicant: 삼성전자주식회사

Inventor： 하재규 ,  황재성 ,  채민철 ,  강윤승 ,  장대현 ,  이주범 ,  엄경하

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L21/76838 ,  H01L21/31144 ,  H01L21/3213 ,  H01L21/67063

Abstract: A method for manufacturing a non-volatile memory device is provided to prevent a gate structure from being damaged by performing two etching processes to expose a drain region and a source region. A tunnel oxide layer(112), a first conductive layer(114), a dielectric layer(116), and a second conductive layer(118) are successively formed on a substrate(100). A first mask pattern(120) is formed on the second conductive layer. Preliminary gate structures to expose a part with a drain region of the substrate are formed by etching the tunnel oxide layer, the first conductive layer, the dielectric layer, and the second conductive layer using the first mask pattern as an etching mask. A second mask pattern with an opening part to expose a part of an upper surface of the preliminary gate structures is formed by etching the first mask pattern partially. Gate structures to expose a part with a source region of the substrate are formed by etching the preliminary gate structures using the second mask pattern as the etching mask.

Abstract translation: 提供一种用于制造非易失性存储器件的方法，以通过执行两个蚀刻工艺来防止栅极结构被损坏以暴露漏极区域和源极区域。 在衬底（100）上依次形成隧道氧化物层（112），第一导电层（114），电介质层（116）和第二导电层（118）。 在第二导电层上形成第一掩模图案（120）。 通过使用第一掩模图案作为蚀刻掩模蚀刻隧道氧化物层，第一导电层，电介质层和第二导电层来形成用于暴露具有衬底的漏极区域的部分的初步栅极结构。 通过部分地蚀刻第一掩模图案，形成具有用于暴露预选栅极结构的上表面的一部分的开口部分的第二掩模图案。 通过使用第二掩模图案作为蚀刻掩模蚀刻预选栅极结构来形成用于暴露具有衬底的源极区域的部分的栅极结构。

公开(公告)号：KR1020080067126A

公开(公告)日：2008-07-18

申请号：KR1020070004311

申请日：2007-01-15

Applicant: 삼성전자주식회사

Inventor： 조우진 ,  황재성 ,  권성운 ,  서준 ,  채민철 ,  강윤승

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  H01L21/76877 ,  H01L21/823475 ,  H01L27/1108

Abstract: A method for manufacturing an SRAM having a contact structure is provided to reduce etch errors and to improve efficiency of an etch process by reducing an aspect ratio. A first bulk transistor is formed on a semiconductor substrate(100). A first insulating layer(110) is formed on the substrate. A lower semiconductor plug is connected to a source region of the first bulk transistor through the first insulating layer. A first lower thin film transistor is formed on the first insulating layer. A second insulating layer(126) is formed on the substrate having the first lower thin film transistor. An upper semiconductor plug is connected to the lower semiconductor plug through the second insulating layer. A first upper thin film transistor is formed on the second insulating layer. A third insulating layer(136) is formed on the substrate. A grounding line contact hole is formed by patterning the first to third insulating layers and the upper/lower semiconductor plugs. A first node contact hole is formed to expose drain regions of the bulk transistor and the first lower thin film transistor and the source region of the first upper thin film transistor. The grounding line contact hole and the first node contact hole are filled with a grounding line plug and a first node contact plug.

Abstract translation: 提供一种用于制造具有接触结构的SRAM的方法，以减少蚀刻误差并通过减小纵横比来提高蚀刻工艺的效率。 第一体晶体管形成在半导体衬底（100）上。 在基板上形成第一绝缘层（110）。 下半导体插头通过第一绝缘层连接到第一体晶体管的源极区域。 第一下部薄膜晶体管形成在第一绝缘层上。 在具有第一下薄膜晶体管的基板上形成第二绝缘层（126）。 上半导体插头通过第二绝缘层连接到下半导体插头。 第一上薄膜晶体管形成在第二绝缘层上。 在基板上形成第三绝缘层（136）。 通过图案化第一至第三绝缘层和上/下半导体插塞形成接地线接触孔。 形成第一节点接触孔，以暴露体晶体管和第一下部薄膜晶体管的漏极区域以及第一上部薄膜晶体管的源极区域。 接地线接触孔和第一节点接触孔填充有接地线插头和第一节点接触插头。