公开(公告)号：KR100500581B1

公开(公告)日：2005-07-18

申请号：KR1020030010815

申请日：2003-02-20

Applicant: 삼성전자주식회사

Inventor： 이우성 ,  김봉현 ,  한명식 ,  정은국

IPC: H01L21/8238

CPC classification number: H01L21/28035 ,  H01L21/2652 ,  H01L21/82345

Abstract: 액티브 피팅 불량을 감소시키면서 게이트 전극을 형성하는 방법이 개시되어 있다. 액티브 및 필드 영역이 구분된 반도체 기판상에 게이트 절연막 및 폴리실리콘막을 형성한다. 상기 폴리실리콘막 상에 이온 주입에 의한 폴리실리콘막의 손상을 감소시키는 버퍼막을 형성한다. 상기 버퍼막상의 이온 주입 영역으로 불순물 이온을 주입하여, 상기 폴리실리콘막을 도전성 폴리실리콘막으로 형성한다. 상기 도전성 폴리실리콘막의 소정부위를 순차적으로 식각하여 게이트 전극을 형성한다. 상기 버퍼막에 의해 폴리실리콘막의 손상이 최소화되어 액티브 피팅 불량이 감소된다.

公开(公告)号：KR1020030002382A

公开(公告)日：2003-01-09

申请号：KR1020010037959

申请日：2001-06-29

Applicant: 삼성전자주식회사

Inventor： 한명식

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66545

Abstract: PURPOSE: A method for forming a gate electrode of a semiconductor device and a method for fabricating a non-volatile memory device by using the same are provided to form a gate electrode for reducing a resistant difference between resistances. CONSTITUTION: A conductive layer is formed on a substrate(100). A dielectric layer is formed on the conductive layer. A polysilicon layer is formed on the dielectric layer. A hard mask layer is formed on the polysilicon layer. A hard mask pattern is formed by etching the hard mask. A gate structure is formed by stacking a gate oxide layer pattern, a conductive layer pattern(102a), a dielectric layer pattern(104a), a polysilicon layer pattern(106a), and a hard mask pattern. A low density source/drain region(112) is formed by using the gate structure as an ion implant mask. A gate spacer is formed on a sidewall of the gate structure. An upper face of the polysilicon layer pattern(106a) is exposed by removing the hard mask pattern. The first part of the gate spacer is projected by removing the hard mask pattern. The polysilicon layer pattern(106a) and the second part of the gate spacer(114b) are planarized by removing the first part of the gate spacer. A stopping layer is formed along an upper face of the polysilicon layer pattern(106a), a sidewall of the gate spacer(114b), and a surface of the semiconductor substrate(100). An interlayer dielectric is formed on the whole surface of the above structure. The polysilicon layer pattern(106a) is exposed by performing a planarization process. A gate electrode is formed by depositing a metal silicide layer(120) on an exposed portion of the polysilicon layer pattern(106a).

Abstract translation: 目的：提供一种用于形成半导体器件的栅电极的方法和使用该方法制造非易失性存储器件的方法，以形成用于降低电阻之间的电阻差的栅电极。 构成：在基板（100）上形成导电层。 在导电层上形成介电层。 在电介质层上形成多晶硅层。 在多晶硅层上形成硬掩模层。 通过蚀刻硬掩模形成硬掩模图案。 通过堆叠栅极氧化物层图案，导电层图案（102a），电介质层图案（104a），多晶硅层图案（106a）和硬掩模图案来形成栅极结构。 通过使用栅极结构作为离子注入掩模来形成低密度源极/漏极区（112）。 栅极间隔件形成在栅极结构的侧壁上。 通过去除硬掩模图案来暴露多晶硅层图案（106a）的上表面。 通过去除硬掩模图案来投影栅极间隔物的第一部分。 通过去除栅极间隔物的第一部分来平坦化多晶硅层图案（106a）和栅极间隔物（114b）的第二部分。 沿着多晶硅层图案（106a）的上表面，栅极间隔物（114b）的侧壁和半导体衬底（100）的表面形成阻挡层。 在上述结构的整个表面上形成层间电介质。 通过进行平坦化处理使多晶硅层图案（106a）露出。 通过在多晶硅层图案（106a）的暴露部分上沉积金属硅化物层（120）形成栅电极。

公开(公告)号：KR1020080016106A

公开(公告)日：2008-02-21

申请号：KR1020060077757

申请日：2006-08-17

Applicant: 삼성전자주식회사

Inventor： 한명식 ,  이승재 ,  정대혁 ,  성충기

IPC: H01L21/304 ,  H01L21/8247

Abstract: A chemical mechanical polishing method and a method of fabricating a flash memory device using the same are provided to form an interlayer dielectric, of which a thickness distribution variation is locally small. A substrate(100) including a silicon oxide layer(120) is prepared, in which a first upper portion of the silicon oxide layer is positioned at a first height, and a second upper portion is positioned at a second height lower than the first height. The silicon oxide layer is subjected to chemical mechanical polishing by using a ceria slurry comprising a ceria polishing agent of 0.5 to 3 wt%, an anion surfactant of 0.8 to 2.0 wt%, and water, in which the first upper portion is polished at a first polishing speed, and the second upper portion is polished at a second polishing speed lower than the first polishing speed.

Abstract translation: 提供化学机械抛光方法和制造使用其的闪速存储器件的方法以形成层间电介质，其中厚度分布变化局部较小。 制备包括氧化硅层（120）的基板（100），其中氧化硅层的第一上部位于第一高度，并且第二上部部分位于比第一高度低的第二高度 。 通过使用包含0.5〜3重量％的二氧化铈抛光剂，0.8〜2.0重量％的阴离子表面活性剂和0.8重量％的阴离子表面活性剂的二氧化铈浆料，将氧化硅层进行化学机械研磨，其中第一上部在 第一抛光速度，并且以比第一抛光速度低的第二抛光速度抛光第二上部。

公开(公告)号：KR100674896B1

公开(公告)日：2007-01-26

申请号：KR1020000043008

申请日：2000-07-26

Applicant: 삼성전자주식회사

Inventor： 한명식 ,  김경현

IPC: H01L21/76

CPC classification number: H01L21/76232

Abstract: 트렌치를 절연물로 채운 반도체 장치의 평탄화를 위한 화학 및 기계적 연마를 실시함에 있어 연마 저지막으로 폴리실리콘을 사용하고, 열산화 공정을 실시하여 트렌치 내벽뿐만아니라 폴리실리콘층 측벽에도 산화막 스페이서를 형성하는 단계와 활성 영역을 오픈하기 위해 폴리실리콘층을 제거할 경우 산화막에 대해 10 내지 20의 선택비를 갖도록 에치백 하는 제 1 단계와 산화막에 대해 50 내지 100 선택비를 갖도록 에치백하는 제 2단계 에치백 공정을 실시하는 단계를 포함하는 소자분리방법이 개시되어, 필드 리세스 마진 확보 및 패드 산화막의 피팅 억제 효과를 얻을 수 있다.
연마 저지막, CMP, 폴리실리콘

公开(公告)号：KR100437089B1

公开(公告)日：2004-06-23

申请号：KR1020010028360

申请日：2001-05-23

Applicant: 삼성전자주식회사

Inventor： 한명식 ,  홍창기

IPC: H01L21/304

CPC classification number: B24B37/30

Abstract: Disclosed is a polishing head of a chemical and mechanical polishing apparatus uniformly polishing a wafer. The polishing head has a body defining at least one air passage therein through which air is introduced into and exhausted from the polishing head. The body is movable upward and downward. An air pressure distributing member is mounted to a lower portion of the body for distributing a pressure of the air supplied through the air passage. A membrane is mounted to enclose a lower surface of the air pressure distributing member so as to be expanded and shrunk by the pressure of the air supplied through the air pressure distributing member. A surface of the air pressure distributing member makes contact with a back surface of a wafer. An air pressure compensating member makes uniformly the pressure that is applied to central and edge portions of the wafer which makes contact with the membrane. Since the air pressure compensating member applies to the edge portion of the wafer, the air pressure is compensated so that the uniform air pressure is applied to the wafer. Thus, the wafer is uniformly polished.

Abstract translation: 公开了一种均匀抛光晶片的化学和机械抛光设备的抛光头。 抛光头具有限定至少一个空气通道的主体，空气通过所述至少一个空气通道被引入抛光头并从抛光头排出。 身体可以上下移动。 气压分配部件安装到主体的下部，用于分配通过气道供应的空气的压力。 安装膜以包围空气压力分配构件的下表面，从而通过由空气压力分配构件供应的空气的压力膨胀和收缩。 气压分配构件的表面与晶片的背面接触。 气压补偿构件均匀地施加施加到与膜接触的晶片的中心部分和边缘部分的压力。 由于气压补偿部件适用于晶片的边缘部分，所以气压得到补偿，从而均匀的气压施加到晶片上。 因此，晶片被均匀抛光。

公开(公告)号：KR100420120B1

公开(公告)日：2004-03-02

申请号：KR1020010031676

申请日：2001-06-07

Applicant: 삼성전자주식회사

Inventor： 한명식 ,  김경현 ,  이용탁

IPC: H01L27/105

CPC classification number: H01L27/11502 ,  H01L21/3212 ,  H01L23/544 ,  H01L27/10894 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device having a capacitor with a high dielectric constant layer includes a groove for an alignment key is formed together with a contact hole on a substrate; a conductive layer of tungsten is formed to fill the contact hole and cover the inner surface of the groove; a capping layer for use as an oxygen barrier is stacked on the conductive layer of tungsten; a planarization process is performed using CMP to leave the capping layer and the conductive layer of tungsten covering the inner surface of the groove to form a contact plug filling the contact hole; a capacitor bottom electrode layer is stacked to contact the top surface of the contact plug; a high dielectric constant layer is stacked on the bottom electrode layer; and an oxidation treatment is performed at a high temperature to crystallize the high dielectric constant layer.

Abstract translation: 一种制造具有高介电常数层的电容器的半导体器件的方法，所述半导体器件包括用于对准键的沟槽与衬底上的接触孔一起形成; 形成钨的导电层以填充接触孔并覆盖沟槽的内表面; 用作氧气阻挡层的覆盖层堆叠在钨的导电层上; 使用CMP进行平坦化工艺以使覆盖层和覆盖沟槽内表面的钨导电层形成填充接触孔的接触插塞; 电容器底部电极层被堆叠以接触接触插塞的顶表面; 高介电常数层堆叠在底部电极层上; 并且在高温下进行氧化处理以使高介电常数层结晶。

公开(公告)号：KR1020020090370A

公开(公告)日：2002-12-05

申请号：KR1020010028360

申请日：2001-05-23

Applicant: 삼성전자주식회사

Inventor： 한명식 ,  홍창기

IPC: H01L21/304

CPC classification number: B24B37/30

Abstract: PURPOSE: A polishing head of a CMP(Chemical Mechanical Polishing) apparatus is provided to polish uniformly a wafer by improving a structure of the polishing head. CONSTITUTION: A surface of a wafer(W) is contacted with a polishing pad. A back face of the wafer(W) is contacted with a polishing head(32). A main body(34) is formed with a housing(36), a base(38), and a retainer ring(40). The base(38) is used for supporting the housing(36). The retainer ring(40) is installed at an edge of a lower portion of the base(38) in order to prevent an escape of the wafer. The housing(36) is connected with a drive portion. The housing(36) has a circular upper face and a circular lower face. The housing(36) includes the first tube(42a). The second and the third tubes(42b,42c) are formed at a predetermined position apart from the first tube(42a). A base(38) is used for supporting the housing(36). The first chamber(44) is formed between the housing(36) and the base(38). A perforate plate(46) is installed at a lower portion of the main body(34). A plurality of through-holes(46a) are formed on the perforate plate(46). A separation plate(48) is formed between the base(38) and the perforate plate(46). An air cushion(50) is installed on an edge portion of the perforate plate(46). A membrane(52) is formed on a lower face of the perforate plate(46).

Abstract translation: 目的：提供CMP（化学机械抛光）装置的抛光头，通过改善抛光头的结构来均匀地抛光晶片。 构成：将晶片（W）的表面与抛光垫接触。 晶片（W）的背面与抛光头（32）接触。 主体（34）形成有壳体（36），基座（38）和保持环（40）。 基座（38）用于支撑壳体（36）。 保持环（40）安装在基部（38）的下部的边缘处，以防止晶片逸出。 壳体（36）与驱动部分连接。 壳体（36）具有圆形的上表面和圆形的下表面。 壳体（36）包括第一管（42a）。 第二和第三管（42b，42c）形成在离开第一管（42a）的预定位置处。 基座（38）用于支撑壳体（36）。 第一室（44）形成在壳体（36）和基座（38）之间。 穿孔板（46）安装在主体（34）的下部。 在穿孔板（46）上形成多个通孔（46a）。 在基座（38）和穿孔板（46）之间形成分隔板（48）。 气垫（50）安装在穿孔板（46）的边缘部分上。 在穿孔板（46）的下表面上形成膜（52）。

公开(公告)号：KR100829594B1

公开(公告)日：2008-05-14

申请号：KR1020060098498

申请日：2006-10-10

Applicant: 삼성전자주식회사

Inventor： 성충기 ,  정대혁 ,  한명식

IPC: C09K3/14

CPC classification number: H01L21/31053 ,  C09G1/02 ,  C09K3/1463 ,  H01L27/115 ,  H01L27/11521

Abstract: A method for fabricating a semiconductor memory device is provided to improve uniformity in the thickness of a polysilicon layer and to reduce damages on the polysilicon layer caused by polishing particles by using a chemical mechanical slurry composition having a high polishing rate to a silicon oxide layer, thereby improving the reliability of the semiconductor device. A method for fabricating a semiconductor memory device comprises the steps of: forming a polysilicon pattern(108) on a semiconductor wafer(100); etching the wafer exposed to the polysilicon pattern to form trenches(109) on the wafer; forming a silicon oxide layer covering the polysilicon pattern with the trenches embedded therein; polishing the silicon oxide layer with a chemical mechanical polishing(CMP) slurry composition to expose the polysilicon pattern and to form a separator for a device, wherein the CMP slurry composition comprises 0.1-3.5 wt% of seria as a polishing agent, 0.01-0.10 wt% of a non-ionic surfactant adsorbed on the surface of the polysilicon layer during CMP to form a protective layer, 0.5-3.5 wt% of polyacrylic acid and the balance amount of water; and forming a structure having a gate dielectric and a conductive pattern on the wafer. In the CMP slurry composition, the non-ionic surfactant has a tri-block structure containing a first polyethylene oxide repeating unit, polypropylene oxide repeating unit and a second polyethylene oxide repeating unit, wherein each of the first polyethylene oxide and the second polyethylene oxide has a HLB(hydrophilic lipophilic balance) value of 10-15, and the polypropylene oxide has a HLB value of 28-32.

Abstract translation: 提供一种用于制造半导体存储器件的方法，以通过使用具有高抛光速率的氧化硅层的化学机械浆料组合物来改善多晶硅层的厚度的均匀性并减少由抛光颗粒引起的对多晶硅层的损伤， 从而提高半导体器件的可靠性。 一种用于制造半导体存储器件的方法包括以下步骤：在半导体晶片（100）上形成多晶硅图案（108）; 蚀刻暴露于多晶硅图案的晶片以在晶片上形成沟槽（109）; 形成覆盖多晶硅图案的氧化硅层，其中嵌有沟槽; 用化学机械抛光（CMP）浆料组合物抛光氧化硅层以暴露多晶硅图案并形成用于器件的隔板，其中CMP浆料组合物包含0.1-3.5重量％的作为抛光剂的丝网，0.01-0.10 在CMP期间吸附在多晶硅层的表面上的非离子表面活性剂的重量％形成保护层，0.5-3.5重量％的聚丙烯酸和余量的水; 以及在所述晶片上形成具有栅极电介质和导电图案的结构。 在CMP浆料组合物中，非离子表面活性剂具有包含第一聚环氧乙烷重复单元，聚环氧丙烷重复单元和第二聚环氧乙烷重复单元的三嵌段结构，其中第一聚环氧乙烷和第二聚环氧乙烷各自具有 HLB（亲水亲油平衡）值为10-15，聚环氧丙烷的HLB值为28-32。

公开(公告)号：KR1020070063071A

公开(公告)日：2007-06-19

申请号：KR1020050122887

申请日：2005-12-14

Applicant: 삼성전자주식회사

Inventor： 한명식 ,  황인석 ,  김은영

IPC: H01L21/027

Abstract: A method for manufacturing a semiconductor device is provided to reduce the generation of failure and to improve the reliability by restraining the damage of an alignment key. A semiconductor substrate is divided into a memory cell region(C) and a peripheral region(P), wherein the peripheral region. A plurality of predetermined structures with the same height are formed within the memory cell region and peripheral region. At this time, the generation of a stepped portion is restrained at a boundary between the peripheral region and memory cell region. A metal line(225) is formed within the memory cell region and an alignment key(230) is formed within the peripheral region. A stepped portion compensating pad is formed on the substrate when the predetermined structures are formed within the peripheral region.

Abstract translation: 提供一种制造半导体器件的方法，以通过抑制对准键的损坏来减少故障的产生和提高可靠性。 半导体衬底被分成存储单元区域（C）和外围区域（P），其中周边区域。 在存储单元区域和外围区域内形成具有相同高度的多个预定结构。 此时，在周边区域和存储单元区域之间的边界处限制阶梯部分的产生。 金属线（225）形成在存储单元区域内，并且在周边区域内形成对准键（230）。 当在周边区域内形成预定结构时，在基板上形成台阶部分补偿焊盘。

公开(公告)号：KR1020120095693A

公开(公告)日：2012-08-29

申请号：KR1020110015165

申请日：2011-02-21

Applicant: 삼성전자주식회사

Inventor： 배진우 ,  황인석 ,  한명식 ,  박세정 ,  조성민 ,  고영호 ,  홍의관

IPC: H01L21/304

CPC classification number: H01L21/31053 ,  H01L21/76819

Abstract: PURPOSE: A semiconductor device having a planarized insulation layer and a forming method thereof are provided to prevent first and second planarized insulation layers from being damaged by preventing a physical stress from being applied to a stress concentration area of a first insulation layer. CONSTITUTION: A substrate(100) having a first section(A) and a second section(B) adjacent each other. A structure(110) is formed on the top of the substrate within the first section. A first insulation layer is formed on the substrate having the structure. The first insulation layer comprises a first top surface, an inclined side wall(130S), and a second top surface(130TB). A second insulation layer is formed on the first insulation layer.

Abstract translation: 目的：提供一种具有平坦化绝缘层及其形成方法的半导体器件，以通过防止物理应力施加到第一绝缘层的应力集中区域来防止第一和第二平坦化绝缘层受损。 构成：具有彼此相邻的第一部分（A）和第二部分（B）的基底（100）。 在第一部分内的基板的顶部上形成结构（110）。 在具有该结构的基板上形成第一绝缘层。 第一绝缘层包括第一顶表面，倾斜侧壁（130S）和第二顶表面（130TB）。 在第一绝缘层上形成第二绝缘层。