公开(公告)号：KR101481573B1

公开(公告)日：2015-01-14

申请号：KR1020080012611

申请日：2008-02-12

Applicant: 삼성전자주식회사

Inventor： 이종원 ,  홍창기 ,  한상엽

IPC: C09K3/14

CPC classification number: H01L21/3212 ,  C09G1/02 ,  C09K3/1463

Abstract: 본 발명은 화학적 기계적 연마용 슬러리 조성물 및 이를 이용한 화학적 기계적 연마 방법에 관한 것으로서, 더욱 구체적으로는 적어도 하나의 인산기(PO
4
3- ) 또는 인산수소기(HPO
4
2- )를 포함하는 인산염인 제 1 연마억제제와 술폰기(-SO
3 H) 또는 황산기(-OSO
3 H)를 갖는 탄소수 2 내지 10의 탄화수소 화합물인 제 2 연마억제제를 포함하는 화학적 기계적 연마용 슬러리 조성물 및 이를 이용한 화학적 기계적 연마 방법에 관한 것이다. 본 발명의 화학적 기계적 연마용 슬러리 조성물 및 이를 이용한 화학적 기계적 연마 방법을 사용하면 SiN와의 선택비를 현저히 개선할 수 있다.
슬러리, 화학적 기계적 연마, CMP, 선택비, pH

公开(公告)号：KR100829616B1

公开(公告)日：2008-05-14

申请号：KR1020060134399

申请日：2006-12-27

Applicant: 삼성전자주식회사

Inventor： 임종흔 ,  홍창기 ,  윤보언 ,  윤성규 ,  최석헌 ,  한상엽

IPC: H01L21/336 ,  H01L23/12

CPC classification number: H01L21/02675 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/78

Abstract: A method for forming a channel silicon layer and a method for manufacturing a stack type semiconductor device are provided to improve operation performance of the transistor formed on a channel silicon film by improving a thickness uniformity of the channel silicon film. A first single crystal silicon film(110) having a protruded portion is formed on an upper surface of a single crystal silicon substrate. A passivation film(112) is formed on the upper surface of the first single crystal silicon film. The first single crystal silicon film and the passivation film are primarily polished, such that a portion of the first single crystal silicon film and a portion of the passivation film are removed from the exposed portion and a second single crystal silicon film and a passivation film pattern are formed. The passivation film pattern is removed. The second single crystal silicon film is polished to form a channel silicon film.

Abstract translation: 提供一种形成沟道硅层的方法和叠层型半导体器件的制造方法，以通过改善沟道硅膜的厚度均匀性来改善形成在沟道硅膜上的晶体管的操作性能。 在单晶硅衬底的上表面上形成具有突出部分的第一单晶硅膜（110）。 在第一单晶硅膜的上表面上形成钝化膜（112）。 主要抛光第一单晶硅膜和钝化膜，使得第一单晶硅膜的一部分和钝化膜的一部分从曝光部分去除，第二单晶硅膜和钝化膜图案 形成。 去除钝化膜图案。 第二单晶硅膜被抛光以形成通道硅膜。

公开(公告)号：KR1020080037333A

公开(公告)日：2008-04-30

申请号：KR1020060104277

申请日：2006-10-26

Applicant: 삼성전자주식회사

Inventor： 임종흔 ,  윤보언 ,  윤성규 ,  최석헌 ,  한상엽 ,  홍창기

IPC: H01L21/304

Abstract: A polishing device and a polishing method are provided to prevent a back side of the wafer from being scratched by contacting only an edge of the wafer, on which a semiconductor chip is not formed, with a polishing head. A polishing device for preventing scratch of a wafer comprises a polishing pad(36), a platen(40), and a polishing head(30). The polishing pad polishes the wafer(32). The platen fixes the polishing pad and rotates the polishing pad. The polishing head includes a bending portion formed at an edge thereof. The polishing head absorbs the wafer in a vacuum state so that only edge parts, in which a pattern of the wafer is not formed, contact with the bending portion. A tape for protecting a circuit is attached to an edge of the wafer.

Abstract translation: 提供抛光装置和抛光方法，以通过仅将未形成半导体芯片的晶片的边缘与抛光头接触来防止晶片的背面被划伤。 用于防止晶片划伤的抛光装置包括抛光垫（36），压板（40）和抛光头（30）。 抛光垫抛光晶片（32）。 压板固定抛光垫并旋转抛光垫。 抛光头包括在其边缘处形成的弯曲部分。 抛光头在真空状态下吸收晶片，使得只有没有形成晶片的图案的边缘部分与弯曲部分接触。 用于保护电路的磁带附接到晶片的边缘。

公开(公告)号：KR1020090062757A

公开(公告)日：2009-06-17

申请号：KR1020070130190

申请日：2007-12-13

Applicant: 삼성전자주식회사

Inventor： 이종원 ,  한상엽 ,  홍창기 ,  윤보언 ,  이재동

IPC: H01L21/283

CPC classification number: H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

Abstract: A method for manufacturing a semiconductor device is provided to improve a shoulder margin of a capping pattern by forming an upper part of the capping pattern to cover a gate pattern with a planarized profile. An element isolation film(112) defining an active area is formed in a semiconductor substrate(110). A gate insulating layer, a gate conductive film and a mask film are formed on a semiconductor substrate. The mask pattern having an upper profile of the rounded shape is formed by patterning the mask film. The gate pattern is formed by patterning the gate conductive film and the gate insulating film. The gate pattern is comprised between a gate insulating pattern(114) and a gate electrode(116). The upper part and the sidewall of the gate pattern are covered with the capping pattern. An interlayer insulating film(124) is formed to expose the upper part of the capping pattern. The capping pattern with the planarized upper profile is formed by polishing the interlayer insulating film and the capping pattern.

Abstract translation: 提供一种用于制造半导体器件的方法，通过形成覆盖图案的上部以覆盖具有平坦化轮廓的栅极图案来改善封盖图案的肩部边缘。 在半导体衬底（110）中形成限定有源区的元件隔离膜（112）。 在半导体衬底上形成栅极绝缘层，栅极导电膜和掩模膜。 通过对掩模膜进行图案化而形成具有圆形形状的上轮廓的掩模图案。 栅极图案通过对栅极导电膜和栅极绝缘膜进行图案化而形成。 栅极图案包括在栅极绝缘图案（114）和栅极电极（116）之间。 栅极图案的上部和侧壁被覆盖图案覆盖。 形成层间绝缘膜（124）以露出封盖图案的上部。 通过抛光层间绝缘膜和封盖图案形成具有平坦化上表面的封盖图案。

公开(公告)号：KR100806351B1

公开(公告)日：2008-02-27

申请号：KR1020070016450

申请日：2007-02-16

Applicant: 삼성전자주식회사

Inventor： 임종흔 ,  홍창기 ,  윤보언 ,  윤성규 ,  최석헌 ,  한상엽

IPC: H01L21/76

CPC classification number: H01L21/76229 ,  H01L21/3212

Abstract: A method for fabricating a semiconductor device is provided to minimize a dishing phenomenon at a planarization process for a crystalline semiconductor layer formed in a peripheral region and/or a test device group region. A pattern having trenches(203a,203b) is formed on a semiconductor substrate(200) to expose the substrate, and then a semiconductor layer is formed to bury the trenches. The semiconductor layer is primarily planarized when the pattern is not exposed. A crystalline semiconductor layer is formed on the primarily planarized semiconductor layer by performing an epitaxial growth process. The crystalline semiconductor layer is secondarily planarized to form a crystalline semiconductor pattern. The substrate has a first region and a second region wider than the first region.

Abstract translation: 提供了一种用于制造半导体器件的方法，以便在形成在周边区域和/或测试器件组区域中的结晶半导体层的平坦化处理期间最小化凹陷现象。 在半导体衬底（200）上形成具有沟槽（203a，203b）以露出衬底的图案，然后形成半导体层以埋设沟槽。 当图案不暴露时，半导体层主要是平面化的。 通过进行外延生长工艺，在主要平坦化的半导体层上形成晶体半导体层。 晶体半导体层被二次平坦化以形成晶体半导体图案。 衬底具有比第一区域宽的第一区域和第二区域。

公开(公告)号：KR1020090003985A

公开(公告)日：2009-01-12

申请号：KR1020070067842

申请日：2007-07-06

Applicant: 삼성전자주식회사

Inventor： 이종원 ,  한상엽 ,  홍창기 ,  이재동

IPC: C09K3/14 ,  H01L21/304

CPC classification number: H01L21/31053 ,  C09G1/02 ,  H01L29/66583 ,  H01L29/66795 ,  H01L29/7851

Abstract: A slurry composition for polishing silicon nitride is provided to polish a silicon nitride film with high polishing selectivity, compared with a silicon oxide film and to be usefully applied to a process of manufacturing a semiconductor where the selective removal of a silicon nitride film is requested. A slurry composition for polishing silicon nitride comprises the first oxide polishing inhibitor 0.01-10 weight%, abrasive 0.01-10 weight% and extra water. The silicon nitride polishing slurry composition has the pH of 1-4. A polishing method of the silicon nitride film comprises a step for forming a silicon oxide film on a substrate; a step for forming a silicon nitride film on the silicon oxide film; and a step for polishing the silicon nitride film until the silicon oxide film is exposed, by using a slurry composition for polishing a silicon nitride containing the first oxide polishing inhibitor including polyacrylic acid, abrasive and water.

Abstract translation: 提供了一种用于研磨氮化硅的浆料组合物，与氧化硅膜相比具有高抛光选择性的氮化硅膜抛光，并且可用于制造需要选择性去除氮化硅膜的半导体工艺。 用于研磨氮化硅的浆料组合物包括0.01-10重量％的第一氧化物抛光抑制剂，0.01-10重量％的磨料和额外的水。 氮化硅抛光浆料组合物的pH为1-4。 氮化硅膜的研磨方法包括在基板上形成氧化硅膜的工序; 在氧化硅膜上形成氮化硅膜的工序; 以及通过使用含有包含聚丙烯酸，磨料和水的第一氧化物抛光抑制剂的氮化硅的研磨用浆料组合物，研磨氮化硅膜直到氧化硅膜露出的步骤。

公开(公告)号：KR1020080051269A

公开(公告)日：2008-06-11

申请号：KR1020060122019

申请日：2006-12-05

Applicant: 삼성전자주식회사

Inventor： 임종흔 ,  홍창기 ,  윤보언 ,  윤성규 ,  최석헌 ,  배대록 ,  한상엽

IPC: H01L21/8229

Abstract: A method of forming a silicon channel layer and a method of manufacturing a stack memory device are provided to improve the yield of the device by forming the silicon channel layer with minimized thickness distribution variations. A second substrate(126) jointed to a first substrate(100) is prepared, and then a polishing stop layer(130) having polishing selectivity different from a silicon(140) is formed on the second substrate. A silicon layer is formed on the polishing stop layer to cover a damaged edge region of the second substrate at an ion cutting process. The silicon layer is removed by a first chemical mechanical polishing process until the surface of the polishing stop layer is exposed. The polishing stop layer is removed, and then the second substrate is polished by a second chemical mechanical polishing process to form the second substrate as a silicon channel layer of the first substrate.

Abstract translation: 提供一种形成硅沟道层的方法和制造堆叠存储器件的方法，以通过以最小的厚度分布变化形成硅沟道层来提高器件的产量。 准备与第一基板（100）接合的第二基板（126），然后在第二基板上形成具有与硅（140）不同的抛光选择性的抛光停止层（130）。 在离子切割处理中，在抛光停止层上形成硅层以覆盖第二基板的损坏边缘区域。 通过第一化学机械抛光工艺去除硅层，直到抛光停止层的表面露出。 除去抛光停止层，然后通过第二化学机械抛光工艺抛光第二衬底，以形成作为第一衬底的硅沟道层的第二衬底。

公开(公告)号：KR1020080010537A

公开(公告)日：2008-01-31

申请号：KR1020060070629

申请日：2006-07-27

Applicant: 삼성전자주식회사

Inventor： 임종흔 ,  홍창기 ,  윤보언 ,  윤성규 ,  한상엽

IPC: H01L21/027 ,  H01L21/32

CPC classification number: G03F7/0002 ,  H01L21/32135

Abstract: A method for forming a fine pattern is provided to form a fine pattern without distortion by performing an imprint method and an electrochemical mechanical polishing process. A method for forming a fine pattern comprises the steps of: preparing a substrate having a conductive film; forming an electro-shielding pattern on the conductive film, wherein the electro-shielding pattern partially exposes the conductive film; and forming a conductive pattern by performing an electrochemical mechanical polishing process for the exposed parts of the conductive film to be removed. The electro-shielding pattern includes Alkanethiol and is coated with Alkanethiol in a monolayer or a multilayer.

Abstract translation: 提供形成精细图案的方法以通过执行压印方法和电化学机械抛光工艺形成没有变形的精细图案。 形成精细图案的方法包括以下步骤：制备具有导电膜的衬底; 在导电膜上形成电屏蔽图案，其中电屏蔽图案部分地暴露导电膜; 以及通过对待除去的导电膜的暴露部分进行电化学机械抛光工艺来形成导电图案。 电屏蔽图案包括烷硫醇并且在单层或多层中涂覆有烷硫醇。

公开(公告)号：KR1020080003616A

公开(公告)日：2008-01-08

申请号：KR1020060062069

申请日：2006-07-03

Applicant: 삼성전자주식회사

Inventor： 윤성규 ,  한상엽 ,  홍창기 ,  윤보언 ,  이재동 ,  박진구 ,  홍의관

IPC: H01L21/304

Abstract: A silica slurry containing a hydro peroxide for CMP(Chemical Mechanical Polishing) of semiconductor devices is provided to reduce generation of organic defects and to improve productivity and yield of the semiconductor devices by making a silicon surface have hydrophilicity after completing the CMP. A silica slurry for CMP of semiconductor devices includes fumed silica particles. A wafer is introduced into a CMP equipment(S10). The wafer is polished by using the silica slurry containing a hydro peroxide(S20). The wafer is cleaned by using a cleaning solution containing hydrofluoric acid(S30). The wafer is cleaned by using deionized water(S40). The wafer is dried(S50). The wafer is withdrawn from the CMP equipment(S60). The fumed silica particles are 0.1 to 50 wt% of a total slurry. A silical particle is over 10 wt% of the total slurry. The hydro peroxide is 0.1 to 3 vol%.

Abstract translation: 提供含有用于半导体器件的CMP（化学机械抛光）的过氧化氢的二氧化硅浆料，以通过在完成CMP之后使硅表面具有亲水性来减少有机缺陷的产生并提高半导体器件的生产率和产率。 用于半导体器件的CMP的二氧化硅浆料包括热解二氧化硅颗粒。 将晶片引入到CMP设备中（S10）。 通过使用含有过氧化氢的二氧化硅浆料对晶片进行抛光（S20）。 使用含有氢氟酸的清洗液清洗晶片（S30）。 用去离子水清洗晶片（S40）。 将晶片干燥（S50）。 从CMP设备中取出晶片（S60）。 热解法二氧化硅颗粒为总泥浆的0.1-50重量％。 硅质颗粒占总浆料的10重量％以上。 过氧化氢为0.1〜3体积％。

公开(公告)号：KR101406888B1

公开(公告)日：2014-06-30

申请号：KR1020070130190

申请日：2007-12-13

Applicant: 삼성전자주식회사

Inventor： 이종원 ,  한상엽 ,  홍창기 ,  윤보언 ,  이재동

IPC: H01L21/283

CPC classification number: H01L21/76897 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L29/6653

Abstract: 반도체 소자의 제조 방법이 제공된다. 이 방법은 기판 상에 게이트 패턴을 형성하는 것, 게이트 패턴의 상부 및 측벽을 덮는 캡핑 패턴을 형성하는 것, 기판 상에 캡핑 패턴의 상부를 노출하는 층간 절연막을 형성하는 것, 및 화학적 기계적 연마 방식으로 캡핑 패턴 및 층간 절연막을 연마하여 평탄화된 상부 프로파일을 갖는 캡핑 패턴을 형성하는 것을 포함한다.
콘택, 자기 정렬, 마스크, 캡핑, 마진