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公开(公告)号：KR1020040024154A
公开(公告)日：2004-03-20
申请号：KR1020020055679
申请日：2002-09-13
Applicant: 삼성전자주식회사
Inventor： 허근
IPC: H01L21/205
Abstract: PURPOSE: High density plasma chemical vapor deposition(CVD) equipment capable of controlling generation of particles on the edge of a semiconductor wafer is provided to control a defect on the edge of a semiconductor wafer due to plasma and reaction gas by installing a clamp between the wafer and the plasma so that the clamp overlaps the edge of the wafer. CONSTITUTION: An inner space of a predetermined size is defined by the outer wall(310) of a chamber. The semiconductor wafer(200) is placed on a susceptor(320) in the chamber. A gas supply unit is so disposed to confront the upper surface of the semiconductor wafer. The clamp(360) is so disposed between the plasma on the semiconductor wafer and the semiconductor wafer to overlap the edge of the semiconductor wafer.
Abstract translation: 目的：提供能够控制半导体晶片边缘产生颗粒的高密度等离子体化学气相沉积（CVD）设备，以通过在等离子体和反应气体之间安装夹具来控制由于等离子体和反应气体导致的半导体晶片边缘的缺陷 晶片和等离子体，使得钳位件与晶片的边缘重叠。 构成：预定尺寸的内部空间由腔室的外壁（310）限定。 半导体晶片（200）被放置在腔室中的基座（320）上。 气体供给单元被设置为面对半导体晶片的上表面。 夹具（360）设置在半导体晶片上的等离子体和半导体晶片之间以与半导体晶片的边缘重叠。
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公开(公告)号：KR1020060037563A
公开(公告)日：2006-05-03
申请号：KR1020040086557
申请日：2004-10-28
Applicant: 삼성전자주식회사
IPC: H01L21/31
CPC classification number: H01L21/02252 , H01L21/02274 , H01L21/3065
Abstract: 본 발명은 고밀도 플라즈마 절연막을 형성시 플라즈마 충격에 의한 금속이온의 발생을 방지할 수 있는 고밀도 플라즈마 절연막의 형성방법을 제공한다. 그 방법은 반응챔버 내의 반도체 기판 상으로 공급된 반응가스를 리모트 플라즈마 발생기를 이용하여 플라즈마화시키고, 플라즈마화된 반응가스를 반도체 기판에 접촉시켜 제1 절연막을 형성한 다음, 상기 반응챔버 내로 공급된 스퍼터용 식각가스를 상기 리모트 플라즈마 발생기를 이용하여 플라즈마화 시킨 후 상기 반도체 기판의 표면을 스퍼터 식각하여 상기 제1 절연막을 소정 두께만큼 제거한다.
고밀도 플라즈마, 리모트, 절연막, 스퍼터 식각-
公开(公告)号：KR1020020018476A
公开(公告)日：2002-03-08
申请号：KR1020000051801
申请日：2000-09-02
Applicant: 삼성전자주식회사
IPC: H01L21/76
Abstract: PURPOSE: A method for forming an isolation region of a semiconductor device is provided to shorten an interval of time for forming the isolation region, by reducing processes for forming a trench oxide layer and annealing an insulation material to one process. CONSTITUTION: A silicon oxide layer(120) is formed on a semiconductor substrate(100). A predetermined portion of the silicon oxide layer and the semiconductor substrate under the predetermined portion are continuously etched to form a trench. An insulation material(160) is filled in the trench. The semiconductor substrate of the sidewall and bottom of the trench filled with the insulation material is oxidized to form a trench oxide layer(180) on the sidewall and bottom of the trench. The insulation material and the silicon oxide layer remaining on the semiconductor substrate are continuously polished by a mechanical polishing method until the surface of the semiconductor substrate is exposed, so that the isolation region is formed.
Abstract translation: 目的：提供一种用于形成半导体器件的隔离区域的方法，通过减少用于形成沟槽氧化物层的工艺和将绝缘材料退火到一个工艺来缩短用于形成隔离区域的时间间隔。 构成：在半导体衬底（100）上形成氧化硅层（120）。 氧化硅层和预定部分下方的半导体衬底的预定部分被连续蚀刻以形成沟槽。 绝缘材料（160）填充在沟槽中。 填充有绝缘材料的沟槽的侧壁和底部的半导体衬底被氧化以在沟槽的侧壁和底部上形成沟槽氧化物层（180）。 残留在半导体基板上的绝缘材料和氧化硅层通过机械抛光法连续抛光，直到半导体衬底的表面露出，从而形成隔离区。
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公开(公告)号：KR1020000065321A
公开(公告)日：2000-11-15
申请号：KR1019990011469
申请日：1999-04-01
Applicant: 삼성전자주식회사
IPC: H01L21/027
Abstract: PURPOSE: A method for preventing a lifting of a photoresist pattern is provided to increase an adhesion between a photoresist pattern and a material layer and to prevent the photoresist pattern from being lifted in a subsequent wet etch process by forming a thin nitride layer on a hydrophilic material layer. CONSTITUTION: In a method for preventing a lifting of a photoresist pattern when a material layer(100) having a hydrophilic property is wet-etched by using a photoresist pattern(106) as a mask, a thin material layer(104) is formed on the material layer to increase an adhesion between the photoresist pattern and the material layer.
Abstract translation: 目的：提供防止光致抗蚀剂图案提升的方法以增加光致抗蚀剂图案和材料层之间的粘附性，并且防止光致抗蚀剂图案在随后的湿法蚀刻工艺中被提升，通过在亲水层上形成薄的氮化物层 材料层。 构成：在通过使用光致抗蚀剂图案（106）作为掩模对具有亲水性的材料层（100）进行湿式蚀刻时，防止光致抗蚀剂图案的提升的方法中，将薄材料层（104）形成在 材料层以增加光致抗蚀剂图案和材料层之间的粘合力。
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公开(公告)号：KR102220445B1
公开(公告)日：2021-02-25
申请号：KR1020190078909
申请日：2019-07-01
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
Abstract: 실시예의반도체소자는기판과, 상기기판상에배치된절연층과, 상기절연층상에배치된문턱전압조절층과, 상기문턱전압조절층상에배치된제1 반도체층과, 상기문턱전압조절층상에배치되어상기제1 반도체층의일부를덮는제2 반도체층을포함할수 있다. 실시예에따른부성미분저항소자는문턱전압조절층을형성함으로써, 게이트전압으로피크전압을소자의동작범위내에서자유롭게조절할수 있는효과가있다.
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Patent Agency Ranking
公开(公告)号：KR1020210005333A
公开(公告)日：2021-01-14
申请号：KR1020190078909
申请日：2019-07-01
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
Abstract: 실시예의반도체소자는기판과, 상기기판상에배치된절연층과, 상기절연층상에배치된문턱전압조절층과, 상기문턱전압조절층상에배치된제1 반도체층과, 상기문턱전압조절층상에배치되어상기제1 반도체층의일부를덮는제2 반도체층을포함할수 있다. 실시예에따른부성미분저항소자는문턱전압조절층을형성함으로써, 게이트전압으로피크전압을소자의동작범위내에서자유롭게조절할수 있는효과가있다.
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公开(公告)号：KR1020150142374A
公开(公告)日：2015-12-22
申请号：KR1020140071069
申请日：2014-06-11
Applicant: 삼성전자주식회사 , 고려대학교 산학협력단
IPC: H01L29/786 , H01L21/336
CPC classification number: H01L29/7869 , H01L29/78606 , H01L29/78618
Abstract: 산화물층및 양자점층으로이루어진채널을포함하는트랜지스터가개시된다. 개시된트랜지스터는백 게이트기판과, 상기기판상의게이트절연층과, 상기게이트절연층상에서산화물층과, 반도체나노층으로이루어진적층구조의채널층과, 상기채널층의양단과각각연결된소스전극및 드레인전극을포함한다. 상기반도체나노층은양자점층또는반도체나노와이어층일수 있다.
Abstract translation: 公开了包括包含氧化物层和量子点层的沟道的晶体管。 所公开的晶体管包括：背栅基板; 基板上的栅极绝缘层; 在所述栅绝缘层上具有包括所述氧化物层和半导体纳米层的叠层结构的沟道层; 以及分别与沟道层的两端连接的源电极和漏电极。 半导体纳米层可以是量子点层或半导体纳米线层。
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公开(公告)号：KR1020060019106A
公开(公告)日：2006-03-03
申请号：KR1020040067588
申请日：2004-08-26
Applicant: 삼성전자주식회사
Inventor： 허근
IPC: H01L21/205
Abstract: 고밀도 플라즈마 증착막의 형성 방법을 제공한다. 이 방법은 반도체기판 상에 제 1 물질막 패턴들을 형성하고, 상기 제 1 물질막 패턴들이 형성된 반도체기판을 고밀도 플라즈마 공정 챔버로 로딩한 후, 상기 고밀도 플라즈마 공정 챔버에 제 1 소스 가스 및 제 2 소스 가스를 함께 공급하면서 상기 제 1 물질막 패턴들이 형성된 반도체기판 상에 제 2 물질막을 증착하는 단계를 포함한다.
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公开(公告)号：KR1020000059316A
公开(公告)日：2000-10-05
申请号：KR1019990006799
申请日：1999-03-02
Applicant: 삼성전자주식회사
Inventor： 허근
IPC: H01L21/31
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to prevent boron and phosphorus from extracting in reflow process, and reduce a step of patterns. CONSTITUTION: A method for manufacturing a semiconductor device comprises the steps of: providing a semiconductor device with a conductive pattern(20) having a step formed thereon; forming a first BPSG(boron phosphorus silicate glass) film on the whole surface of the semiconductor device; forming a spacer(23) on a side wall of the conductive pattern having a step by etching the whole surface of the first BPSG film; forming a second BPSG film(24) on the whole surface of the semiconductor substrate including the spacer; and heat-treating the second BPSG film. The spacer is formed on a lower portion of the second BPSG film. The heat-treating step is performed at a temperature in range of 800 to 900°C.
Abstract translation: 目的：提供一种用于制造半导体器件的方法，以防止在回流过程中提取硼和磷，并且减少图案的步骤。 构成：制造半导体器件的方法包括以下步骤：为半导体器件提供其上形成有台阶的导电图案（20）; 在半导体器件的整个表面上形成第一BPSG（硼磷硅玻璃）膜; 通过蚀刻第一BPSG膜的整个表面，在具有台阶的导电图案的侧壁上形成间隔物（23）; 在包括间隔物的半导体衬底的整个表面上形成第二BPSG膜（24）; 并对第二BPSG膜进行热处理。 间隔件形成在第二BPSG膜的下部。 热处理步骤在800-900℃的温度范围内进行。
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公开(公告)号：KR1020000026460A
公开(公告)日：2000-05-15
申请号：KR1019980043990
申请日：1998-10-20
Applicant: 삼성전자주식회사
IPC: H01L21/00
Abstract: PURPOSE: A vacuum gauge is provided to minimize an influence on a wafer due to thermal electrons and electromagnetic waves to enhance the yields by forming a connection line having plural curvatures. CONSTITUTION: A wafer(30, 31) is kept in a load lock chamber(16) before being transferred to a process chamber(12). The load lock chamber(16). A vacuum gauge(26) is provided to measure a vacuum degree in the chamber(16). The load lock chamber(16) and the vacuum gauge(26) are connected to prevent an influence due to thermal electrons and electromagnetic waves, and plural connection lines(50) having plural curvatures are formed. The connection lines(50) are twisted in a spiral shape. The vacuum gauge(26) is ionization guage.
Abstract translation: 目的：提供真空计，以最小化由于热电子和电磁波对晶片的影响，以通过形成具有多个曲率的连接线来提高产量。 构成：在转移到处理室（12）之前，将晶片（30,31）保持在负载锁定室（16）中。 负载锁定室（16）。 提供真空计（26）以测量腔室（16）中的真空度。 负载锁定室（16）和真空计（26）被连接以防止由于热电子和电磁波的影响，并且形成具有多个曲率的多个连接线（50）。 连接线（50）以螺旋状扭曲。 真空计（26）是电离计。
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