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公开(公告)号：KR1020160149105A
公开(公告)日：2016-12-27
申请号：KR1020150086179
申请日：2015-06-17
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L27/146 , H01L29/786
CPC classification number: H01L31/0336 , H01L31/032 , H01L31/1129
Abstract: 광전자소자가개시된다. 개시된광전자소자는산화물반도체층, 및이 산화물반도체층과스택구조를이루는반도체성이차원물질층;을포함한다.
Abstract translation: 公开了一种光电子器件。 所公开的光电子器件包括氧化物半导体层和形成具有氧化物半导体层的堆叠结构的半导体二维（2D）材料层。
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公开(公告)号：KR101514600B1
公开(公告)日：2015-04-23
申请号：KR1020140036699
申请日：2014-03-28
Applicant: 성균관대학교산학협력단
IPC: H01L21/205 , H01L21/316
CPC classification number: H01L21/02175 , H01L21/0228 , H01L21/02395 , H01L21/02472 , H01L21/02554 , H01L21/0262
Abstract: 반도체소자제조방법이개시된다. 반도체소자제조방법은 p-형반도체기판의표면에제1 원자층증착공정을이용하여산화아연박막을형성하는단계; 및상기산화아연박막상부에제2 원자층증착공정을이용하여고유전율(high-K) 절연막을형성하는단계를포함한다.
Abstract translation: 公开了半导体器件的制造方法。 制造半导体器件的方法包括以下步骤：在p型半导体衬底的表面上通过使用第一原子层沉积工艺形成氧化锌薄膜; 并且通过使用第二原子层沉积工艺在氧化锌薄膜的上部形成高介电率（高K）绝缘膜。
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公开(公告)号：KR101348059B1
公开(公告)日：2014-01-03
申请号：KR1020120073819
申请日：2012-07-06
Applicant: 성균관대학교산학협력단
IPC: H01L29/786 , H01L21/336
CPC classification number: H01L29/78696 , H01L29/24 , H01L29/66742
Abstract: The present invention relates to a thin film transistor comprising oxygen plasma treated channel layer and a method of manufacturing the same. According to the embodiment of the present invention, the thin film transistor includes a substrate; a source/drain electrode on the substrate; a channel layer made of a chalcogenides-based material on the substrate and the source/drain electrode; a dielectric layer; and a gate electrode. [Reference numerals] (S410) Step of providing a substrate; (S420) Step of forming a source/drain electrode on the substrate; (S430) Step of depositing a channel layer made of a chalcogenides-based material on the substrate and the source/drain electrode; (S440) Step of oxygen plasma treating the top of the channel layer; (S450) Step of depositing a dielectric layer on the top of the oxygen plasma treated channel layer; (S460) Step of forming a gate electrode on a dielectric
Abstract translation: 本发明涉及包含氧等离子体处理的沟道层的薄膜晶体管及其制造方法。 根据本发明的实施例，薄膜晶体管包括基板; 基底上的源极/漏极; 在衬底和源/漏电极上由硫属元素化物基材料制成的沟道层; 电介质层; 和栅电极。 （参考号）（S410）提供基板的工序; （S420）在基板上形成源极/漏极的工序; （S430）在基板和源极/漏极上沉积由硫属元素化物系材料构成的沟道层的工序; （S440）氧等离子体处理通道层顶部的工序; （S450）在氧等离子体处理的沟道层的顶部上沉积电介质层的步骤; （S460）在电介质上形成栅电极的步骤
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公开(公告)号：KR102198344B1
公开(公告)日：2021-01-04
申请号：KR1020180174284
申请日：2018-12-31
Applicant: 연세대학교 산학협력단 , 성균관대학교산학협력단
IPC: H01L25/065 , H01L23/13 , H01L23/29 , H01L23/48 , H01L21/321 , H01L27/146
Abstract: 본발명은 3 차원적층소자제조방법에관한것이다. 본발명의일 실시예에따른 3 차원적층소자제조방법은제 1 베이스층, 상기제 1 베이스층상의제 1 희생층, 상기제 1 희생층상의적어도하나이상의제 1 소자가형성된제 1 반도체층 및상기제 1 반도체층을덮어상기제 1 소자를절연시키는제 1 페시베이션층을포함하는제 1 디바이스기판을준비하는단계; 상기제 1 디바이스기판의상기페시베이션층과대향되도록, 접합표면을갖는핸들기판을준비하는단계; 상기제 1 디바이스기판과상기핸들기판을서로접합시켜제 1 접합기판적층체를형성하는단계; 및상기제 1 접합기판적층체의상기제 1 희생층을선택적으로제거하여, 상기제 1 디바이스기판의제 1 반도체층과상기제 1 페시베이션층을상기핸들기판측으로전달하여상기제 1 반도체층의저면이노출되도록역전되어상기핸들기판상에접합된제 1 모놀리식소자기판을형성하는단계를포함할수 있다.
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公开(公告)号：KR102106721B1
公开(公告)日：2020-05-06
申请号：KR1020180169742
申请日：2018-12-26
Applicant: 연세대학교 산학협력단 , 성균관대학교산학협력단
IPC: H01L29/66 , H01L21/02 , H01L21/768 , H01L21/8234
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Patent Agency Ranking
公开(公告)号：KR101638978B1
公开(公告)日：2016-07-13
申请号：KR1020090067826
申请日：2009-07-24
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
IPC: H01L29/786
CPC classification number: H01L29/7869
Abstract: 박막트랜지스터및 그제조방법이개시된다. 개시된박막트랜지스터는게이트; 게이트절연막; 제1산화물반도체층및 제2산화물반도체층을포함하는채널층; 상기채널층의양측에각각접촉형성된소스및 드레인;을포함하며, 상기제1산화물반도체층의결정립크기는상기제2산화물반도체층의결정립크기에비해상대적으로크다.
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公开(公告)号：KR1020150081202A
公开(公告)日：2015-07-13
申请号：KR1020140000931
申请日：2014-01-03
Applicant: 삼성전자주식회사 , 성균관대학교산학협력단
CPC classification number: H01B1/04 , C23C16/0281 , C23C16/40 , C23C16/405 , C23C16/45553 , H01L29/1606 , H01L29/513 , H01L29/7781 , Y10T428/265 , Y10T428/30 , B32B9/00 , B32B38/00 , C01B32/00
Abstract: 그래핀층상에형성된물질층을포함하는적층구조체및 그래핀층상에물질층을형성하는방법이개시된다. 개시된적층구조체는그래핀층상에원자층증착법에의하여물질층을형성하고자하는경우, 그래핀층상에선형프리커서를이용하여시드층으로서의중간층을형성시킬수 있다.
Abstract translation: 在本发明中，公开了包括形成在石墨烯层上的材料层的堆叠结构和在石墨烯层上形成线性前置标记的石墨烯层上形成材料层的方法，从而形成中间层作为 当在所公开的堆叠结构中使用原子层沉积方法在石墨烯层上形成材料层时，晶种层。
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公开(公告)号：KR1020140020636A
公开(公告)日：2014-02-19
申请号：KR1020120087793
申请日：2012-08-10
Applicant: 성균관대학교산학협력단
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/04 , G11C13/004 , H01L45/146
Abstract: The present invention relates to a resistive memory device. Particularly, the present invention relates to a resistive memory device comprising a crystalline oxide film and a method for fabricating the same. According to the present invention, the resistive memory device comprising a crystalline oxide film includes a substrate (100); a lower electrode (110) formed on the substrate; a variable resistance layer (120) arranged on the lower electrode; and an upper electrode formed on the variable resistance layer. Here, the variable resistance layer (120) comprises at least two oxide layers (121,122). The at least two oxide layers must include at least one amorphous oxide layer and at least one crystalline oxide layer. [Reference numerals] (AA,CC,122) Amorphous Al_2O_3; (BB,EE,100) Substrate; (DD,121) Amorphous HfO_2
Abstract translation: 本发明涉及电阻式存储器件。 特别地，本发明涉及一种包括结晶氧化物膜的电阻式存储器件及其制造方法。 根据本发明，包括结晶氧化物膜的电阻式存储器件包括衬底（100）; 形成在所述基板上的下电极（110） 布置在下电极上的可变电阻层（120） 以及形成在可变电阻层上的上电极。 这里，可变电阻层（120）包括至少两个氧化物层（121,122）。 至少两个氧化物层必须包括至少一个无定形氧化物层和至少一个结晶氧化物层。 （AA，CC，122）无定形Al_2O_3; （BB，EE，100）底物; （DD，121）无定形HfO_2
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公开(公告)号：KR1020130114824A
公开(公告)日：2013-10-21
申请号：KR1020120037158
申请日：2012-04-10
Applicant: 성균관대학교산학협력단
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L45/04 , H01L45/1233 , H01L45/145
Abstract: PURPOSE: A resistive random access memory device and a manufacturing method thereof are provided to improve the uniformity of a current by including a variable resistive layer. CONSTITUTION: A variable resistive layer (130) is arranged on the upper surface of a first electrode (110) and is composed of a zirconium oxide thin film. A second electrode (120) is arranged on the upper surface of the variable resistive layer. The zirconium oxide thin film is coated with cerium. A part of the variable resistive layer is made of oxide.
Abstract translation: 目的：提供一种电阻随机存取存储器件及其制造方法，通过包括可变电阻层来提高电流的均匀性。 构成：可变电阻层（130）布置在第一电极（110）的上表面上，并由氧化锆薄膜构成。 第二电极（120）布置在可变电阻层的上表面上。 氧化锆薄膜用铈涂覆。 可变电阻层的一部分由氧化物制成。
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公开(公告)号：KR102106720B1
公开(公告)日：2020-05-06
申请号：KR1020180169733
申请日：2018-12-26
Applicant: 연세대학교 산학협력단 , 성균관대학교산학협력단 , 경북대학교 산학협력단 , (재)한국나노기술원
IPC: H01L29/66 , H01L29/78 , H01L21/8234 , H01L21/02 , H01L21/304
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