公开(公告)号：KR101196791B1

公开(公告)日：2012-11-05

申请号：KR1020107017903

申请日：2008-03-13

Applicant: 소이텍

Inventor： 알리베르프레데릭 ,  고댕그웰타즈 ,  랄르망파브리스 ,  랑드뤼디디에 ,  랑드리카린느 ,  샤힌모하마드 ,  마쭈레카를로스

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78603 ,  H01L29/32 ,  H01L29/7841 ,  H01L31/0248

Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.

公开(公告)号：KR1020100113117A

公开(公告)日：2010-10-20

申请号：KR1020107017903

申请日：2008-03-13

Applicant: 소이텍

Inventor： 알리베르프레데릭 ,  고댕그웰타즈 ,  랄르망파브리스 ,  랑드뤼디디에 ,  랑드리카린느 ,  샤힌모하마드 ,  마쭈레카를로스

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78603 ,  H01L29/32 ,  H01L29/7841 ,  H01L31/0248 ,  H01L27/10844

Abstract: Embodiments of the invention relate to substrates comprising a base wafer, an insulating layer and a top semiconductor layer, wherein the insulating layer comprises at least a zone wherein a density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to processes for making such substrates.