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公开(公告)号:KR100392341B1
公开(公告)日:2003-07-23
申请号:KR1020000073846
申请日:2000-12-06
Applicant: 전자부품연구원
IPC: H01P1/203
Abstract: PURPOSE: A band pass filter using a DGS is provided to increase the number of stages and a bandwidth by forming a defected ground structure having a constant pattern at a ground surface of a band pass filter. CONSTITUTION: One stage band pass filter includes micro scrip lines(1,3) of an input/output terminal, a micro scrip line(2), a dielectric substrate(4), and a ground surface(5). The micro scrip line(2) is arranged between the micro scrip lines(1,3). Lower ground surfaces of the micro scrip lines(1,3) are etched to form a defected ground structure(6). The defected ground structure(6) has an LC resonance circuit feature. The defected ground structure(6) is used for a small component such as a multi-layer or a monolithic microwave integrated circuit. A defected ground structure pattern is used in an input/output terminal of an active element.
Abstract translation: 目的:提供使用DGS的带通滤波器,以通过在带通滤波器的接地表面处形成具有恒定图案的缺陷接地结构来增加级数和带宽。 构成:一级带通滤波器包括输入/输出终端,微代码线(2),电介质基片(4)和接地表面(5)的微码线(1,3)。 微码纸线(2)布置在微码纸线(1,3)之间。 微纹理线(1,3)的较低的地面被蚀刻以形成缺陷的地面结构(6)。 缺陷接地结构(6)具有LC谐振电路特征。 缺陷接地结构(6)用于诸如多层或单片微波集成电路的小部件。 在有源元件的输入/输出端子中使用缺陷的接地结构图案。
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公开(公告)号:KR1020000059649A
公开(公告)日:2000-10-05
申请号:KR1019990007417
申请日:1999-03-06
Applicant: 전자부품연구원
IPC: H01F17/00
Abstract: PURPOSE: A laminated transformer for high frequency is provided to ensure high impedance variation rate even in using inductor with a low capacity by using a capacitor. CONSTITUTION: A transformer is comprised of a first inductor(L1), a first capacitor(C1), a second inductor(L2) and a second capacitor(C). The first inductor(L1) has a ceramic sheet(300) which is provided with a ground terminal pattern(301) and a coil pattern(302). The first capacitor(C) has two ceramic sheets(330,340) which are provided with capacitor patterns(331,341), respectively. The second inductor(L2) has a ceramic sheet(350) which is provided with a first input terminal pattern(351) and a coil pattern(352). The second capacitor(C2) has two ceramic sheets(380,390) which are provided with capacitor patterns(381,391). Each sheet has via-holes filled with paste so that the coil patterns and capacity patterns are electrically connected via the conductive paste.
Abstract translation: 目的:提供高频用层压变压器,即使在使用电容器的情况下使用低容量的电感器也能确保高阻抗变化率。 构成:变压器包括第一电感器(L1),第一电容器(C1),第二电感器(L2)和第二电容器(C)。 第一电感器(L1)具有设置有接地端子图案(301)和线圈图案(302)的陶瓷片(300)。 第一电容器(C)具有分别具有电容器图案(331,341)的两个陶瓷片(330,340)。 第二电感器(L2)具有设置有第一输入端子图案(351)和线圈图案(352)的陶瓷片(350)。 第二电容器(C2)具有设置有电容器图案(381,391)的两个陶瓷片(380,390)。 每个片材具有填充有膏体的通孔,使得线圈图案和容量图案经由导电膏电连接。
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公开(公告)号:KR1020020044748A
公开(公告)日:2002-06-19
申请号:KR1020000073846
申请日:2000-12-06
Applicant: 전자부품연구원
IPC: H01P1/203
Abstract: PURPOSE: A band pass filter using a DGS is provided to increase the number of stages and a bandwidth by forming a defected ground structure having a constant pattern at a ground surface of a band pass filter. CONSTITUTION: One stage band pass filter includes micro scrip lines(1,3) of an input/output terminal, a micro scrip line(2), a dielectric substrate(4), and a ground surface(5). The micro scrip line(2) is arranged between the micro scrip lines(1,3). Lower ground surfaces of the micro scrip lines(1,3) are etched to form a defected ground structure(6). The defected ground structure(6) has an LC resonance circuit feature. The defected ground structure(6) is used for a small component such as a multi-layer or a monolithic microwave integrated circuit. A defected ground structure pattern is used in an input/output terminal of an active element.
Abstract translation: 目的:提供使用DGS的带通滤波器,以通过在带通滤波器的地表面处形成具有恒定图案的缺陷接地结构来增加级数和带宽。 构成:一级带通滤波器包括输入/输出端子,微型线路(2),电介质基板(4)和地表面(5)的微秒线(1,3)。 微秒线(2)布置在微型线条(1,3)之间。 蚀刻微片线(1,3)的下表面以形成缺陷的接地结构(6)。 缺陷接地结构(6)具有LC谐振电路特征。 缺陷接地结构(6)用于诸如多层或单片微波集成电路的小部件。 在有源元件的输入/输出端子中使用有缺陷的接地结构图案。
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公开(公告)号:KR100288964B1
公开(公告)日:2001-04-16
申请号:KR1019990007417
申请日:1999-03-06
Applicant: 전자부품연구원
IPC: H01F17/00
Abstract: 이발명의고주파용적층형트랜스포머에서, 다수의제1 세라믹시트에는도전성페이스트가충진된비어홀이각각형성되어있고, 이비어홀을통하여연결되어제1 인덕터를형성하는제1 코일패턴이각각형성되어있다. 그리고, 제2 세라믹시트에는제1 세라믹시트의제1 코일패턴과연결되는제1 캐패시터패턴이형성되어있고, 제3 세라믹시트에는제2 캐패시터패턴이형성되어있으며, 제2 및제3 세라믹시트는서로일정간격을두고형성되어제1 캐패시터를형성한다. 다수의제4 세라믹시트에는비어홀이각각형성되어있고, 이비어홀을통하여제2 인덕터를형성하는제2 코일패턴이각각형성되어있으며, 상기제2 코일패턴은상기제3 세라믹시트의제2 캐패시터패턴과연결된다. 그리고, 제5 세라믹시트에는제2 코일패턴과연결되는제3 캐패시터패턴이형성되어있고, 제6 세라믹시트에는제4 캐패시터패턴이형성되어있으며, 제5 및제6 세라믹시트는서로일정간격을두고형성되어제2 캐패시터를형성한다. 이러한적층형트랜스포머는캐패시터를사용함에따라, 저용량의인덕터를사용하여도높은임피던스변환율을얻을수 있으며, 소형으로제조가가능하고, 제조공정이간단하다.
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