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公开(公告)号：KR1020060094225A
公开(公告)日：2006-08-29
申请号：KR1020050015214
申请日：2005-02-24
Applicant: 연세대학교 산학협력단 , 한국전자통신연구원
IPC: H03M1/10
CPC classification number: H03M1/1028 , H03M1/1033 , H03M1/108 , H03M2201/20 , H03M2201/63 , H03M2201/657
Abstract: 아날로그 테스트 패턴으로 삼각파나 램프 파형을 이용하는 BIST에서 선형성이나 이득의 이상유무를 간단하게 판단할 수 있는 회로로서, N비트의 해상도를 가진 ADC로부터 받은 출력을 한 번 미분하는 수단(미도시)과, 상기 미분수단의 출력신호를 입력받아, N비트의 입력 중 일정한 기울기만을 검사하는데 필요한 하위 비트와, 필요하지 않으면서 부호 비트를 포함한 상위 비트로 나누는 수단과, 상기 상위 비트값을 '0'과 비교하여 일치여부를 출력하는 제1비교수단과, 상기 하위 비트값을 이상값 'A' 및 '0'과 비교하여 그 일치여부를 출력하는 제2비교수단 및 제3비교수단 및 상기 제1~3비교수단에서 출력된 결과에 따라 테스트대상의 상태를 파악하는 수단을 포함하여 구성되는 단순화로직.
BIST, BISC, ADC, 단순화, 미분신호-
公开(公告)号：KR100212481B1
公开(公告)日：1999-08-02
申请号：KR1019960054841
申请日：1996-11-18
Applicant: 한국전자통신연구원 , 주식회사 엘지데이콤
IPC: H04B7/26
Abstract: 본 발명은 하부가 ATM 스위치들로 구성된 이동통신 시스템의 유선 구간에서 연결 재라우팅 방법에 관한 것으로, 종래의 재라우팅 방법의 문제점인 핸드오프 지연 시간을 줄이고 불필요한 사전 연결을 줄이기 위해 다단계 임계치를 갖는 핸드오프 알고리즘을 적용하여 다수의 부영역과 세 개의 방향으로 셀을 구성하여 사전 연결 설정이 필요한 경로와 사전 연결 해제가 필요한 경로를 식별함으로써 망 자원을 효율적으로 사용할 수 있는 다단계 임계치를 갖는 핸드오프 알고리즘을 이용한 연결 재라우팅 방법이 제시된다.
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Patent Agency Ranking
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公开(公告)号：KR1019960013271B1
公开(公告)日：1996-10-02
申请号：KR1019930030898
申请日：1993-12-29
IPC: H04M3/22
Abstract: The method is for providing an intelligent network service. A communication part receives a resource request message from the SSP and transmits it to resource control unit. The resource control part inspects the usability of the resource function requested. If it is not useful, the procedure terminates to be abnormal. If it is useful, the resource control part connects the resource function requested to the user. The resource function part interacts to the user and then cancels the connection. The resource control part sends the result of the interaction to the communication part for converting to the message associated with the protocols.
Abstract translation: 该方法是提供智能网络服务。 通信部件从SSP接收资源请求消息并将其发送到资源控制单元。 资源控制部分检查所请求的资源功能的可用性。 如果没有用，程序终止为异常。 如果有用，则资源控制部分将请求的资源功能连接到用户。 资源功能部分与用户交互，然后取消连接。 资源控制部分将交互结果发送到通信部分，以转换为与协议相关联的消息。
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公开(公告)号：KR1019960011966B1
公开(公告)日：1996-09-06
申请号：KR1019930027361
申请日：1993-12-11
Applicant: 한국전자통신연구원
IPC: H04L12/28
Abstract: receiving a message frame with a start flag by waiting a frame receipt after latching and initializing an assigned node, IPCU(Inter-Processor Communication Unit) address, its group information, and characteristic information of each node with a system driving; checking a presence of forcibly inserted '0' bit to remove and to confirm a node characteristic; extracting an IPCU address from the frame when the node characteristic is lower gateway node to perform "upper gateway node path control" to permit the message frame receipt according to a communication mode, performing a process to wait the frame receipt when a path control is continued; extracting the IPCU address from the frame when the node characteristics is a processor node perform "processor node path control permitted the message frame receipt according to the communication mode by extracting a node address from the frame once again to wait the frame receipt when continuing the path control.
Abstract translation: 通过在系统驱动后锁存和初始化分配的节点，IPCU（处理器间通信单元）地址，其组信息和每个节点的特征信息等待帧接收来接收具有起始标志的消息帧; 检查强制插入的“0”位的存在以去除并确认节点特性; 当节点特性为低级网关节点时，从帧中提取IPCU地址，执行“上网关节点路径控制”，根据通信模式允许消息帧接收，执行路径控制继续等待帧接收的处理 ; 当节点特征为处理器节点时，从帧中提取IPCU地址执行“处理器节点路径控制根据通信模式允许消息帧接收，通过从帧再次提取节点地址以在继续路径时等待帧接收 控制。
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公开(公告)号：KR1019960001084B1
公开(公告)日：1996-01-18
申请号：KR1019920026126
申请日：1992-12-29
IPC: H04M3/22
Abstract: checking whether an alarm is generated in a present node by transmitting a hardwear alarm signal to an FI block when the alarm is generated, reading a present node state, extracting an alarm address of a node indicated by a present node table pointer, and confirming the address of the nodes where the alarm had been generated; if the alarm is generated in the present node in the above step, transferring alarm generation information to a management processor by extracting the address and information from the node table; if the present node table pointer is not the last one after checking the node, extracting the alarm address of the node by regulating the node table indication pointer; and if the present node table pointer is the last one, returning to the first step.
Abstract translation: 通过在产生报警时向FI块发送硬件报警信号，读取当前节点状态，提取由本节点表指针指示的节点的报警地址，并且确认是否在当前节点中生成报警 生成报警的节点的地址; 如果在上述步骤中在当前节点中产生报警，则通过从节点表中提取地址和信息将报警产生信息传送到管理处理器; 如果当前节点表指针不是检查节点后的最后一个指针，则通过调节节点表指示指针来提取节点的报警地址; 并且如果当前节点表指针是最后一个指针，则返回到第一步。
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公开(公告)号：KR1019950013173B1
公开(公告)日：1995-10-25
申请号：KR1019920026101
申请日：1992-12-29
IPC: H04Q11/04
Abstract: The apparatus comprises an upper processor matching unit for matching a universal processor with a peripheral circuit, and transmitting/receiving a control signal therefrom; a universal processor and peripheral circuit for receiving the control signal of the upper processor, performing a function through a common memory unit by means of a single chip processor and peripheral circuit, and sending the overall operations to the upper processor; a common memory unit for communicating with the universal and single chip processor in the interrupt manner; a single chip processor and peripheral circuit for treating the HDLC data from the HDLC treat unit depending upon the command of the universal processor at a high speed, and sending the data to a HDLC treat unit; a HDLC treat unit for transmitting the HDLC data to the TS determined according to the command of the single chip processor and peripheral circuit; a matching circuit for connecting the time switch with the HDLC treat unit through the PCM path; and a clock supply and resetting circuit for providing clocks to be used in the universal and single chip processors, in case of turn on power, resetting the processors, producing the control signal through the common memory unit by means of the universal processor and peripheral circuit and the single chip processor and peripheral circuit, and performing an independent function, regardless of the control signal.
Abstract translation: 该装置包括用于将通用处理器与外围电路匹配的上位处理器匹配单元，以及从其发送/接收控制信号; 用于接收上位处理器的控制信号的通用处理器和外围电路，通过单个芯片处理器和外围电路通过公共存储器单元执行功能，并将整个操作发送到上位处理器; 用于以中断方式与通用和单芯片处理器通信的通用存储器单元; 单芯片处理器和外围电路，用于根据通用处理器的高速命令从HDLC处理单元处理HDLC数据，并将数据发送到HDLC处理单元; HDLC处理单元，用于将HDLC数据发送到根据单芯片处理器和外围电路的命令确定的TS; 用于通过PCM路径将时间开关与HDLC处理单元连接的匹配电路; 以及用于在通用和单芯片处理器中提供时钟的时钟供应和复位电路，在接通电源的情况下，复位处理器，通过通用处理器和外围电路通过公共存储器产生控制信号 和单芯片处理器和外围电路，并且执行独立的功能，而不管控制信号。
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