公开(公告)号：KR1020120072217A

公开(公告)日：2012-07-03

申请号：KR1020100134051

申请日：2010-12-23

Applicant: 한국전자통신연구원

Inventor： 쿠날 ,  한선호 ,  최장홍 ,  어익수 ,  유현규

IPC: H01P1/36

CPC classification number: H01P1/18 ,  H01P1/005 ,  H01P1/22 ,  H03H9/706

Abstract: PURPOSE: A programmable active isolator for cancelation of a leakage is provided to improve the linearity of a whole system by eliminating a leakage of RF signals without using frequency conversion. CONSTITUTION: A main isolating unit(110) is arranged in a main route. A leakage removal unit(120) including a voltage reducer(121) and a phase shifter(122) is arranged in a branch route branched off the main route and removes leaked signals. In the leakage removal unit, the voltage reducer and the phase shifter are integrated into a single chip.

Abstract translation: 目的：提供用于消除泄漏的可编程有源隔离器，通过消除RF信号的泄漏而不使用频率转换来提高整个系统的线性度。 构成：主隔离单元（110）布置在主路线上。 在从主路径分支的分支路径中设置包括减压器（121）和移相器（122）的泄漏去除单元（120），并且去除泄漏的信号。 在泄漏去除单元中，降压器和移相器集成到单个芯片中。

公开(公告)号：KR1020130106733A

公开(公告)日：2013-09-30

申请号：KR1020120028503

申请日：2012-03-20

Applicant: 한국전자통신연구원

Inventor： 쿠날

IPC: H03F1/26 ,  H03F1/32

CPC classification number: H04L27/0002 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/111 ,  H03F2200/294

Abstract: PURPOSE: A low-noise amplifier is provided to remove interference components and noise from a radio frequency (RF) signal without changing frequencies and to improve the linearity of an interference remover and the linearity of a system by suppressing unwanted harmonics. CONSTITUTION: A low-noise amplifier includes a multi-input interference remover (100) which receives multiple input signals (IN1-INn) and outputs a signal where interference components are removed. Multiple gain control blocks (G1-Gn) receive each of the multiple input signals and perform gain control. A combining block (50) combines the output signals of the multiple gain control blocks.

Abstract translation: 目的：提供低噪声放大器，以从频率（RF）信号中消除干扰成分和噪声，无需改变频率，并通过抑制不需要的谐波来提高干扰去除器的线性度和系统的线性度。 构成：低噪声放大器包括多输入干扰去除器（100），其接收多个输入信号（IN1-INn）并输出干扰分量被去除的信号。 多个增益控制块（G1-Gn）接收多个输入信号中的每一个并执行增益控制。 组合块（50）组合多个增益控制块的输出信号。

公开(公告)号：KR1020130068642A

公开(公告)日：2013-06-26

申请号：KR1020110135942

申请日：2011-12-15

Applicant: 한국전자통신연구원

Inventor： 쿠날

IPC: H03K21/00 ,  H03K23/00 ,  H03L7/18

CPC classification number: H03K21/026 ,  H03K21/10

Abstract: PURPOSE: A high speed counter device is provided to reduce power consumed at an upper bit counter and to eliminate a bottleneck phenomenon generated at the upper bit counter. CONSTITUTION: A high speed counter device includes a first counter(10), a second counter(20), and a clock signal generation part. The first counter counts the lower bits of a final output signal according to a first clock signal. The second counter counts the upper bits of the final output signal according to a second clock signal. The clock signal generation part generates the second clock signal from the first clock signal. The second clock signal is synchronized with a frequency lower than the frequency of the first clock signal.

Abstract translation: 目的：提供高速计数器装置，以减少高位计数器消耗的功耗，并消除高位计数器产生的瓶颈现象。 构成：高速计数器装置包括第一计数器（10），第二计数器（20）和时钟信号产生部件。 第一计数器根据第一时钟信号计数最终输出信号的低位。 第二计数器根据第二时钟信号计数最终输出信号的高位。 时钟信号产生部分从第一时钟信号产生第二时钟信号。 第二时钟信号与低于第一时钟信号的频率的频率同步。

公开(公告)号：KR1020120072219A

公开(公告)日：2012-07-03

申请号：KR1020100134054

申请日：2010-12-23

Applicant: 한국전자통신연구원

Inventor： 어익수 ,  김상균 ,  한선호 ,  박미정 ,  김성도 ,  쿠날 ,  유현규

IPC: H04B1/16

CPC classification number: H04B1/30 ,  H03D3/008 ,  H04L25/063

Abstract: PURPOSE: A digital radio frequency reception apparatus is provided to reduce consumption power, area, and development costs by eliminating interference signals in a reception signal outputted from a rational decimator. CONSTITUTION: A mixer(140) eliminates IF(Intermediate Frequency) signals from output signals of a digital signal converter(130). An integer decimator(150) executes the integer decimeter of the phase-separated signal. A DC(Direct Current) offset compensator(160) eliminates DC(Direct Current) component from the processed signals. An IQ mismatch compensator(170) compensates phase errors of quadrature signal and in phase signal for the signal. A rational decimator(180) executes the rational decimation of the phase compensated signal. A channel selecting filter(190) eliminates interference signal from the signal.

Abstract translation: 目的：提供一种数字射频接收装置，通过消除从理性抽取器输出的接收信号中的干扰信号来降低功耗，面积和开发成本。 构成：混合器（140）消除来自数字信号转换器（130）的输出信号的IF（中频）信号。 整数抽取器（150）执行相分离信号的整数分米。 DC（直流）偏移补偿器（160）从处理的信号中消除DC（直流）分量。 IQ失配补偿器（170）补偿信号的正交信号和相位信号的相位误差。 理性抽取器（180）执行相位补偿信号的有理抽取。 信道选择滤波器（190）消除来自该信号的干扰信号。