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1.发明申请OVERERASE CORRECTION FOR FLASH MEMORY WHICH LIMITS OVERERASE AND PREVENTS ERASE VERIFY ERRORS 审中-公开FLASH存储器的更新校正限制更新和预防删除验证错误
公开(公告)号：WO1997015928A1
公开(公告)日：1997-05-01
申请号：PCT/US1996010720
申请日：1996-06-21
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： ADVANCED MICRO DEVICES, INC. , CLEVELAND, Lee , CHANG, Chung, K. , TANG, Yuan , LEONG, Nancy , FLIESLER, Michael , KUO, Tiao-Hua
IPC: G11C16/06
CPC classification number: G11C16/3409 , G11C16/3404 , G11C16/3445
Abstract: An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.
Abstract translation: 一种包括闪存EEPROM存储单元阵列的集成电路，其中在施加每个擦除脉冲之后提供过电压校正。
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2.发明授权OVERERASE CORRECTION FOR FLASH MEMORY WHICH LIMITS OVERERASE AND PREVENTS ERASE VERIFY ERRORS 失效关于修正删除闪存与对照的灭绝与持续LÖSCHPRÜFFEHLERN防治方案
公开(公告)号：EP0857346B1
公开(公告)日：1999-08-11
申请号：EP96921742.1
申请日：1996-06-21
Applicant: ADVANCED MICRO DEVICES INC.
Inventor： CLEVELAND, Lee , CHANG, Chung, K. , TANG, Yuan , LEONG, Nancy , FLIESLER, Michael , KUO, Tiao-Hua
IPC: G11C16/06
CPC classification number: G11C16/3409 , G11C16/3404 , G11C16/3445
Abstract: An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.
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3.发明公开SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE 有权具有灵活的内存BANK分类法同时闪存
公开(公告)号：EP1116239A1
公开(公告)日：2001-07-18
申请号：EP99946599.0
申请日：1999-08-16
Applicant: ADVANCED MICRO DEVICES INC. , FUJITSU LIMITED
Inventor： KUO, Tiao-Hua , KASA, Yasushi , LEONG, Nancy , CHEN, Johnny , VAN BUSKIRK, Michael
Abstract: A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array (20) including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines (28 and 30) each connected to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder (22) connected to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders (24 and 26) are connected to the X-decoder (22). Two Y-decoders (32 and 34) are connected to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.
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4.发明授权SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE 有权具有灵活的内存BANK分类法同时闪存
公开(公告)号：EP1116239B1
公开(公告)日：2002-05-15
申请号：EP99946599.0
申请日：1999-08-16
Applicant: ADVANCED MICRO DEVICES INC. , FUJITSU LIMITED
Inventor： KUO, Tiao-Hua , KASA, Yasushi , LEONG, Nancy , CHEN, Johnny , VAN BUSKIRK, Michael
Abstract: A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array (20) including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines (28 and 30) each connected to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder (22) connected to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders (24 and 26) are connected to the X-decoder (22). Two Y-decoders (32 and 34) are connected to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.
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5.发明公开METHOD OF MAKING FLEXIBLY PARTITIONED METAL LINE SEGMENTS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE 有权工艺制备软SHARED金属线路逐段法同时闪存的运行具有灵活SHARED银行架构
公开(公告)号：EP1116236A1
公开(公告)日：2001-07-18
申请号：EP99942182.9
申请日：1999-08-16
Applicant: ADVANCED MICRO DEVICES INC. , FUJITSU LIMITED
Inventor： KUO, Tiao-Hua , KASA, Yasushi , LEONG, Nancy , CHEN, Johnny , VAN BUSKIRK, Michael
Abstract: A method of forming flexibly partitioned metal line segments (10 and 12) for separate memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture comprises the steps of providing a basic metal layer (2) comprising a plurality of basic metal layer segments (2a, 2b, 2c, ...2j) separated by a plurality of gaps (6a, 6b, 6c, ...6i), each of the gaps having a predefined gap interval length, and providing a metal option layer (8) comprising a plurality of metal option layer segments on the basic metal layer (2), the metal option layer segments overlapping the gaps between the basic metal layer segments but leaving one of the gaps open, to form the metal line segments for the separate memory banks.
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Patent Agency Ranking6.发明授权METHOD OF MAKING FLEXIBLY PARTITIONED METAL LINE SEGMENTS FOR A SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE 有权工艺制备软SHARED金属线路逐段法同时闪存的运行具有灵活SHARED银行架构
公开(公告)号：EP1116236B1
公开(公告)日：2002-05-15
申请号：EP99942182.9
申请日：1999-08-16
Applicant: ADVANCED MICRO DEVICES INC. , FUJITSU LIMITED
Inventor： KUO, Tiao-Hua , KASA, Yasushi , LEONG, Nancy , CHEN, Johnny , VAN BUSKIRK, Michael
Abstract: A method of forming flexibly partitioned metal line segments (10 and 12) for separate memory banks in a simultaneous operation flash memory device with a flexible bank partition architecture comprises the steps of providing a basic metal layer (2) comprising a plurality of basic metal layer segments (2a, 2b, 2c, ...2j) separated by a plurality of gaps (6a, 6b, 6c, ...6i), each of the gaps having a predefined gap interval length, and providing a metal option layer (8) comprising a plurality of metal option layer segments on the basic metal layer (2), the metal option layer segments overlapping the gaps between the basic metal layer segments but leaving one of the gaps open, to form the metal line segments for the separate memory banks.
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7.发明授权
公开(公告)号：EP1116238B1
公开(公告)日：2003-02-26
申请号：EP99942281.9
申请日：1999-08-16
Applicant: ADVANCED MICRO DEVICES INC. , FUJITSU LIMITED
Inventor： KUO, Tiao-Hua , Patent Administration Department of Fujitsu Ltd , LEONG, Nancy , CHEN, Johnny , VAN BUSKIRK, Michael
Abstract: A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option (18), a bank selector encoder (2) connected to receive a memory partition indicator signal from the memory boundary option (18), and a bank selector decoder (3) connected to receive a bank selector code from the bank selector encoder (2). The decoder (3), upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.
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8.发明授权
公开(公告)号：EP1125301B1
公开(公告)日：2002-10-16
申请号：EP99941220.8
申请日：1999-08-16
Applicant: ADVANCED MICRO DEVICES INC. , FUJITSU LIMITED
Inventor： KUO, Tiao-Hua , KASA, Yasushi , LEONG, Nancy , CHEN, Johnny , VAN BUSKIRK, Michael
Abstract: A decoding circuit (54) for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder (44), a lower bank decoder (58), an upper bank decoder (56), and a plurality of flexibly partitioned conductive lines connected between the upper and lower bank decoders (56 and 58). The flexibly partitioned conductive lines (60, 62, 64, ... 74) provide a plurality of bank address pre-decoding bits for the X-decoder (44) to row decode the memory cells along the respective word lines in the memory array (20). The memory array (20) includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are connected to two Y-decoders (32 and 34) which provide column decoding for the memory cells in the upper and lower memory banks.
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9.发明公开
公开(公告)号：EP1125301A1
公开(公告)日：2001-08-22
申请号：EP99941220.8
申请日：1999-08-16
Applicant: ADVANCED MICRO DEVICES INC. , FUJITSU LIMITED
Inventor： KUO, Tiao-Hua , KASA, Yasushi , LEONG, Nancy , CHEN, Johnny , VAN BUSKIRK, Michael
Abstract: A decoding circuit (54) for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder (44), a lower bank decoder (58), an upper bank decoder (56), and a plurality of flexibly partitioned conductive lines connected between the upper and lower bank decoders (56 and 58). The flexibly partitioned conductive lines (60, 62, 64, ... 74) provide a plurality of bank address pre-decoding bits for the X-decoder (44) to row decode the memory cells along the respective word lines in the memory array (20). The memory array (20) includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are connected to two Y-decoders (32 and 34) which provide column decoding for the memory cells in the upper and lower memory banks.
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10.发明公开
公开(公告)号：EP1116238A1
公开(公告)日：2001-07-18
申请号：EP99942281.9
申请日：1999-08-16
Applicant: ADVANCED MICRO DEVICES INC. , FUJITSU LIMITED
Inventor： KUO, Tiao-Hua , Patent Administration Department of Fujitsu Ltd , LEONG, Nancy , CHEN, Johnny , VAN BUSKIRK, Michael
Abstract: A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option (18), a bank selector encoder (2) connected to receive a memory partition indicator signal from the memory boundary option (18), and a bank selector decoder (3) connected to receive a bank selector code from the bank selector encoder (2). The decoder (3), upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.
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