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    SAMPLE WORKING DEVICE
    1.
    发明专利
    SAMPLE WORKING DEVICE 失效

    公开(公告)号：JPH0845466A

    公开(公告)日：1996-02-16

    申请号：JP17530394

    申请日：1994-07-27

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： MIKI ICHIJI

    IPC: G01B7/34 ,  G01N1/28 ,  G01N21/17 ,  G01N37/00 ,  G01Q10/02 ,  G01Q10/04 ,  G01Q60/10 ,  G01Q80/00 ,  H01J37/30

    Abstract: PURPOSE:To provide a measurement probe for a scanning probe microscope used for observing a sample in a working chamber of the sample that does not interfere supply of a material for working to the sample surface in working the sample. CONSTITUTION:A probe 20 of a scanning tunneling microscope 10 for observing a sample surface is provided in a working chamber 30 of the sample S. The probe 20 is attached to piezoelectric effect elements 13 for a probe drive by a probe holder 14 along (z) direction perpendicular to the sample surface. The piezoelectric effect elements 13 are so formed that, when a prescribed strength of voltage is applied from a (z) direction drive circuit 48 at the first polarity, the probe 20 is turned out to the sample along the (z) direction and when a prescribed size output voltage is applied at the polarity inverse to the first polarity from a probe lead circuit 23 by switching a switch circuit 22, the probe 20 is drawn back in a retreat position along the (z) direction. The retreat position is so set that a material M for working which is supplied to the sample surface is not interfered by the probe 20.

    CRYSTAL GROWTH METHOD
    3.
    发明专利
    CRYSTAL GROWTH METHOD 失效

    公开(公告)号：JPH04154114A

    公开(公告)日：1992-05-27

    申请号：JP27999390

    申请日：1990-10-18

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： SAKAMOTO KUNIHIRO ,  SAKAMOTO SUMINORI ,  MIKI ICHIJI

    IPC: H01L29/04 ,  H01L21/20

    Abstract: PURPOSE:To laminate fine line structures whose cycle is different by a method wherein a part near a plane (001) at an Si or Ge single-crystal substrate is kept in such a way that its temperature can be controlled, the growth operation of a crystal is interrupted by controlling the temperature and the crystal is grown by being separated into two monoatomic layers. CONSTITUTION:An Si substrate 100 is housed in a vacuum chamber; and it is kept at a required temperature by using a heater or a cooling device. When both orientations of the substrate are close to , step edges are situated along and two kinds of monoatomic-layer steps are produced. A monoatomic-layer step SA where atoms on the terrace on the step, unbonded hands and a step end are vertical and a step SB which is parallel to it are arranged. A temperature is controlled; the Ge monoatomic-layer step SB is used as a starting point; a 0.5 atomic layer is formed selectively; and the steps SA, SB are separated. When the growth interruption time is set sufficiently, the interval between the steps GA, SB is returned to an interval before the growth operation. The step SB is used again as a starting point; a selective growth operation is executed in the same manner; and the steps are separated. When the operation is repeated, it is possible to form the extremely fine line structure of Ge in which the diffusion and the adhesion rate of Ge are controlled and which uses the interval between the monoatomic-layer steps SA, SB of the Si substrate is used as a cycle.

    COOLING PIPING FACILITY
    4.
    发明专利
    COOLING PIPING FACILITY 失效

    公开(公告)号：JP2001050692A

    公开(公告)日：2001-02-23

    申请号：JP22185099

    申请日：1999-08-05

    Applicant: AGENCY IND SCIENCE TECHN ,  MIKI ICHIJI

    Inventor： MIKI ICHIJI

    IPC: F25D17/02 ,  F28G7/00

    Abstract: PROBLEM TO BE SOLVED: To clean the inside of a cooling pipeline without stopping an apparatus. SOLUTION: An apparatus having a cooling pipeline 5 is provided with a degassing unit 2 for removing dissolved gas, and an ultrasonic oscillator 3 for clean the inside of the pipeline. The degassing unit 2 previously removes gas dissolved into cooling water and propagation attenuation rate of ultrasonic wave generated from an ultrasonic wave generator comprising an ultrasonic oscillator 3 can be lowered so that the ultrasonic wave can propagate up to the forward end of a long cooling pipeline in an apparatus 4. Consequently, the cooling pipeline in the apparatus can be cleaned entirely. Furthermore, generation of rust or bacteria causing clogging can be suppressed by degassing cooling water through the degassing unit 2 thereby reducing oxygen in the cooling water.

    SEMICONDUCTOR DEVICE AND WIRING METHOD IN THE DEVICE
    5.
    发明专利
    SEMICONDUCTOR DEVICE AND WIRING METHOD IN THE DEVICE 失效

    公开(公告)号：JP2000021883A

    公开(公告)日：2000-01-21

    申请号：JP18739098

    申请日：1998-07-02

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： MIKI ICHIJI

    IPC: H01L21/285 ,  H01L21/3205

    Abstract: PROBLEM TO BE SOLVED: To provide a metal thin wire structure, whose wiring width is small in accordance with a new principle by preventing the width of metal wiring from being limited by the resolution of a semiconductor lithography. SOLUTION: At connecting circuit elements A and B, a local distortion is formed on the surface of a semiconductor substrate S or a semiconductor material layer formed on the substrate S, and then a metallic element, such as bismuth, is deposited on the surface. Thus, a metallic element thin wire L positioned by this distortion is formed as a wiring between the circuit elements A and B. Then, this distortion can be formed, based on the structure on the boundary face or end parts of the circuit elements A and B, or based on the defects formed on the surface of the semiconductor substrate or the semiconductor material layer.

    SOLAR CELL
    6.
    发明专利
    SOLAR CELL 失效

    公开(公告)号：JPH06302840A

    公开(公告)日：1994-10-28

    申请号：JP11390593

    申请日：1993-04-16

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： MIKI ICHIJI ,  SAKAMOTO KUNIHIRO ,  SAKAMOTO SUMINORI

    IPC: H01L31/04

    Abstract: PURPOSE:To obtain a solar cell wherein incident light in a long wavelength region is absorbed and photoelectric conversion efficiency is increased by a method wherein a quantum well layer or a superlattice layer is formed in a bonding part. CONSTITUTION:Two semiconductor layers out of an n-type semiconductor layer 2, a p-type semiconductor layer 5 and an i-type semiconductor layer are bonded in a bonding part, and incident light L is photoelectrically converted and taken out as electric power from electrodes 1, 6 connected respectively to the two semiconductor layers. In such a solar cell, a quantum well layer 3 or a superlattice layer is formed in the bonding part. Alternatively, a graded layer which has changed a potential continuously is formed at least in the quantum well layer 3 or the superlattice layer and between the two semiconductor layers. For example, an n-type semiconductor layer 2 and a p-type semiconductor layer 5 in which crystal Si has been doped respectively with As and Ga are formed, a mixed-crystal semiconductor layer in which the composition ratio of Si to Ge is 80% to 20% is formed between them and it is used as a quantum well layer 3.

    LOCAL ETCHING METHOD AND DEVICE
    7.
    发明专利
    LOCAL ETCHING METHOD AND DEVICE 失效

    公开(公告)号：JPH0860383A

    公开(公告)日：1996-03-05

    申请号：JP19808094

    申请日：1994-08-23

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： MIKI ICHIJI ,  ANDO ATSUSHI

    IPC: C23F1/02 ,  B23H3/00 ,  C25F3/14 ,  H01L21/30 ,  H01L21/306

    Abstract: PURPOSE: To precisely execute local etching of the surface of a conductive substrate by a small and inexpensive device. CONSTITUTION: A soln. 12 is injected into an electrolytic cell 10 and the conductive substrate 11 to be locally etched at the surface is immersed therein. Voltage to attain the oxidation potential at which the surface of the conductive substrate 11 is electrochemically oxidized is impressed between a reference electrode 13 making electrical contact with the soln. 12 and the conductive substrate 11 by a DC power source 15. The front end of a probe 30 is brought near to the surface of the conductive substrate 11 and the voltage at which the local region of the substrate surface facing the front end of the probe attains reduction potential is impressed between this probe 30 and the conductive substrate 11 by a DC power source 18.

    GROWTH OF CRYSTAL AND DEVICE THEREFOR
    8.
    发明专利
    GROWTH OF CRYSTAL AND DEVICE THEREFOR 失效

    公开(公告)号：JPH0859400A

    公开(公告)日：1996-03-05

    申请号：JP19037394

    申请日：1994-08-12

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： MIKI ICHIJI ,  ANDO ATSUSHI

    IPC: C30B7/12 ,  C30B29/02 ,  C30B29/52 ,  C30B29/68 ,  C30B35/00

    Abstract: PURPOSE: To grow a metallic crystal film on a conductive substrate and to enhance the precision in controlling the thickness of the grown film with this small-sized and inexpensive device. CONSTITUTION: A conductive substrate 11 with a metallic film formed on its surface is placed in an electric cell 10. A soln. 12 contg. a metallic ion to be grown is injected into the cell 10 to dip the substrate 11. The reference electrode 13 and counter electrode 14 are electrically connected in the soln. 12. A switching circuit 17 is closed by a controller 22, and the potential of the substrate is electrochemically controlled by controlling variable DC power sources 15 and 16. Consequently, a metallic crystal film with the minimum growth unit film thickness as the atom layer order is electrodeposited and grown on the substrate 11 surface.

    SEMICONDUCTOR DEVICE ELECTRODE STRUCTURE
    10.
    发明专利
    SEMICONDUCTOR DEVICE ELECTRODE STRUCTURE 失效

    公开(公告)号：JP2000182987A

    公开(公告)日：2000-06-30

    申请号：JP35463698

    申请日：1998-12-14

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： MIKI ICHIJI

    IPC: H01L21/28

    Abstract: PROBLEM TO BE SOLVED: To make electric contact between an electrode and a substrate on the order of atoms by burying a dopant material in the terrace on a semiconductor substrate and laminating a metal layer on the dopant-buried surface rearranged structure. SOLUTION: A dopant surface rearranged structure 12 has a dopant metal material e.g. Bi buried in a topmost layer of the terrace on a semiconductor surface in the form of a buried thin linear structure. On this rearranged structure 12 a metal thin film, e.g. Al thin film 13 is laminated. A semiconductor layer 15 is thinly covered just on the rearranged structure 12 and disposed for avoiding oxidation to prevent the electric conduction from deteriorating due to oxidation of the dopant material. When the dopant material uses Bi, the semiconductor layer 15 pref. uses Si.

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