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    FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING SAME
    1.
    发明专利
    FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING SAME 未知

    公开(公告)号：CA2303471A1

    公开(公告)日：2000-11-28

    申请号：CA2303471

    申请日：2000-03-30

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： SAKAMOTO KUNIHIRO

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/786 ,  H01L29/772

    Abstract: A dual gate structure field-effect transistor is manufactured by forming a trench in an SOI substrate comprised of a semiconductor support substrate, a buried insulation layer formed on the support substrate and an SOI semiconductor layer formed on the insulation layer, so as to extend from an upper surface of the SOI substrate through the SOI semiconductor layer and the buried insulation layer to the semiconductor support substrate, thereby dividing the SOI semiconductor layer into two SOI semiconductor layer regions that form a source electrode and a drain electrode; forming a gate electrode constituted of low resistance material in a portion of the trench in contact with the buried insulation layer, thereby self-aligning with the source electrode and drain electrode; forming a gate insulation layer on the gate electrode in contact with the buried insulation layer around the trench; forming a semiconductor conduction channel layer on the gate insulation layer in contact with the two SOI semiconductor layer regions around the trench; forming an upper gate insulation layer on an upper surface of the semiconductor conduction channel layer and a SOI semiconductor layer inside surface defining the trench; and forming an upper gate electrode in the trench so as to have a bottom surface and side surface covered by the upper gate insulation layer, thereby self-aligning with the gate electrode, source electrode and drain electrode.

    METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE
    4.
    发明专利
    METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JP2001102590A

    公开(公告)日：2001-04-13

    申请号：JP27744499

    申请日：1999-09-29

    Applicant: AGENCY IND SCIENCE TECHN ,  MATSUMOTO KAZUHIKO

    Inventor： MATSUMOTO KAZUHIKO ,  SAKAMOTO KUNIHIRO

    IPC: H01L27/12 ,  H01L21/02 ,  H01L21/336 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To sandwich an electrode material, serving as a lower gate, at the time of wafer bonding using a wafer bonding technology. SOLUTION: A double gate field effect transistor comprises a lower gate electrode 3, a lower gate insulating film 4, a channel layer 5, a gate insulation film 7, and an upper gate electrode 8. An electrode material, serving as a lower gate 3, is sandwiched at the time of wafer bonding using a wafer bonding technology. Other process is similar to existing process for fabricating silicon integrated circuit in the fabrication of a semiconductor device, e.g. a double gate field effect transistor.

    SOLAR CELL
    5.
    发明专利
    SOLAR CELL 失效

    公开(公告)号：JPH06302840A

    公开(公告)日：1994-10-28

    申请号：JP11390593

    申请日：1993-04-16

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： MIKI ICHIJI ,  SAKAMOTO KUNIHIRO ,  SAKAMOTO SUMINORI

    IPC: H01L31/04

    Abstract: PURPOSE:To obtain a solar cell wherein incident light in a long wavelength region is absorbed and photoelectric conversion efficiency is increased by a method wherein a quantum well layer or a superlattice layer is formed in a bonding part. CONSTITUTION:Two semiconductor layers out of an n-type semiconductor layer 2, a p-type semiconductor layer 5 and an i-type semiconductor layer are bonded in a bonding part, and incident light L is photoelectrically converted and taken out as electric power from electrodes 1, 6 connected respectively to the two semiconductor layers. In such a solar cell, a quantum well layer 3 or a superlattice layer is formed in the bonding part. Alternatively, a graded layer which has changed a potential continuously is formed at least in the quantum well layer 3 or the superlattice layer and between the two semiconductor layers. For example, an n-type semiconductor layer 2 and a p-type semiconductor layer 5 in which crystal Si has been doped respectively with As and Ga are formed, a mixed-crystal semiconductor layer in which the composition ratio of Si to Ge is 80% to 20% is formed between them and it is used as a quantum well layer 3.

    METHOD OF CRYSTAL GROWTH
    7.
    发明专利
    METHOD OF CRYSTAL GROWTH 失效

    公开(公告)号：JPH06283432A

    公开(公告)日：1994-10-07

    申请号：JP3454193

    申请日：1993-01-29

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： SAKAMOTO KUNIHIRO ,  MIKI ICHIJI ,  SAKAMOTO SUMINORI

    IPC: C30B23/02 ,  C30B29/68 ,  H01L21/205

    Abstract: PURPOSE:To form a lightly doped crystalline layer with a good heterojunction by forming a bismuth-absorbing layer on a single-crystal silicon substrate, and supplying a source gas over the substrate to grow single-crystal film under the bismuth-absorbing layer. CONSTITUTION:A bismuth-absorbing layer 8 is formed on a silicon substrate 4, and germanium is supplied. The germanium enters under the bismuth- absorbing layer 8, but it is prevented from diffusing. As a result, the three- dimensional growth of germanium is prevented and thus a flat germanium layer 9 is formed on the substrate 4. Silicon is supplied so that it may enter under the bismuth-absorbing layer 8. This prevents the germanium from depositing on the surface, resulting in a good heterojunction. After bismuth is removed, silicon is further supplied to form a flat silicon layer of good crystallinity. According to this method, it is possible to form a lightly doped crystalline layer with a good heterojunction.

    SEMICONDUCTOR DEVICE
    8.
    发明专利
    SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JPH0555551A

    公开(公告)日：1993-03-05

    申请号：JP23873991

    申请日：1991-08-26

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： MATSUMOTO KAZUHIKO ,  HAYASHI YUTAKA ,  ISHII MASAMI ,  SAKAMOTO KUNIHIRO ,  MOROZUMI HIDEHIRO

    IPC: H01L29/205 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737

    Abstract: PURPOSE:To improve the characteristics of a transistor, especially the base resistance, the Early effect, the punch-through voltage and the frequency characteristic by allowing to rapidly increasing the rate of induced charge of the base in a transistor charge induced in a storage layer of the semiconductor surface. CONSTITUTION:When a 15a negative bias is impressed on an n GaAs emitter, holes of majority carriers are stored on an the interface between a p-GaAs collector 55a in which majority carriers are depleted during the unbiased time, and a GaAlAs/AlAs barrier 25a acting as a barrier to the majority carriers (holes) of the p GaAs collector 55a because of wider gap than that of the p GaAs collector 55a, so as to act as a base. Induced charge is a storage layer 35, so that a large amount of holes can be induced by a low emitter.base voltage.

    CRYSTAL GROWTH METHOD
    9.
    发明专利
    CRYSTAL GROWTH METHOD 失效

    公开(公告)号：JPH04154114A

    公开(公告)日：1992-05-27

    申请号：JP27999390

    申请日：1990-10-18

    Applicant: AGENCY IND SCIENCE TECHN

    Inventor： SAKAMOTO KUNIHIRO ,  SAKAMOTO SUMINORI ,  MIKI ICHIJI

    IPC: H01L29/04 ,  H01L21/20

    Abstract: PURPOSE:To laminate fine line structures whose cycle is different by a method wherein a part near a plane (001) at an Si or Ge single-crystal substrate is kept in such a way that its temperature can be controlled, the growth operation of a crystal is interrupted by controlling the temperature and the crystal is grown by being separated into two monoatomic layers. CONSTITUTION:An Si substrate 100 is housed in a vacuum chamber; and it is kept at a required temperature by using a heater or a cooling device. When both orientations of the substrate are close to , step edges are situated along and two kinds of monoatomic-layer steps are produced. A monoatomic-layer step SA where atoms on the terrace on the step, unbonded hands and a step end are vertical and a step SB which is parallel to it are arranged. A temperature is controlled; the Ge monoatomic-layer step SB is used as a starting point; a 0.5 atomic layer is formed selectively; and the steps SA, SB are separated. When the growth interruption time is set sufficiently, the interval between the steps GA, SB is returned to an interval before the growth operation. The step SB is used again as a starting point; a selective growth operation is executed in the same manner; and the steps are separated. When the operation is repeated, it is possible to form the extremely fine line structure of Ge in which the diffusion and the adhesion rate of Ge are controlled and which uses the interval between the monoatomic-layer steps SA, SB of the Si substrate is used as a cycle.

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