公开(公告)号：GB2343976A

公开(公告)日：2000-05-24

申请号：GB0001920

申请日：1997-04-01

Applicant: ALTERA CORP

Inventor： CLIFF RICHARD G ,  HEILE FRANCIS B ,  HUANG JOSEPH ,  LANE CHRISTOPHER F ,  LEE FUNG FUNG ,  MCCLINTOCK CAMERON ,  MENDEL DAVID WOLK ,  NGO NINH D ,  PEDERSEN BRUCE B ,  REDDY SRINIVAS T ,  SUNG CHIAKANG ,  VEENSTRA KERRY ,  WANG BONNIE I-KEH

IPC: H03K19/177

Abstract: Logic modules 22 in a programmable logic array integrated circuit device each include programmable logic feeding a register. Secondary signals such as clocks and clears for the registers can be drawn 120 either from dedicated secondary signal conductors 50e,f or normal region inputs.

公开(公告)号：GB2343976B

公开(公告)日：2000-07-26

申请号：GB0001920

申请日：1997-04-01

Applicant: ALTERA CORP

Inventor： CLIFF RICHARD G ,  HEILE FRANCIS B ,  HUANG JOSEPH ,  LANE CHRISTOPHER F ,  LEE FUNG FUNG ,  MCCLINTOCK CAMERON ,  MENDEL DAVID W ,  NGO NINH D ,  PEDERSEN BRUCE B ,  REDDY SRINIVAS T ,  SUNG CHIAKANG ,  VEENSTRA KERRY ,  WANG BONNIE I

IPC: H03K19/177

公开(公告)号：GB2312065B

公开(公告)日：2000-08-16

申请号：GB9706583

申请日：1997-04-01

Applicant: ALTERA CORP

Inventor： LANE CHRISTOPHER F ,  LEE FUNG FUNG ,  MCCLINTOCK CAMERON ,  WANG BONNIE I-KEH ,  CLIFF RICHARD G ,  HEILE FRANCIS B ,  HUANG JOSEPH ,  MENDEL DAVID WOLK ,  NGO NINH D ,  PEDERSEN BRUCE B ,  REDDY SRINIVAS T ,  SUNG CHIAKANG ,  VEENSTRA KERRY

IPC: H03K19/04 ,  H03K19/177

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

公开(公告)号：GB2312065A

公开(公告)日：1997-10-15

申请号：GB9706583

申请日：1997-04-01

Applicant: ALTERA CORP

Inventor： LANE CHRISTOPHER F ,  LEE FUNG FUNG ,  MCCLINTOCK CAMERON ,  WANG BONNIE I ,  CLIFF RICHARD G ,  HEILE FRANCIS B ,  HUANG JOSEPH ,  MENDEL DAVID WOLK ,  NGO NINH D ,  PEDERSEN BRUCE B ,  REDDY SRINIVAS T ,  SUNG CHIAKANG ,  VEENSTRA KERRY

IPC: H03K19/04 ,  H03K19/177

Abstract: A programmable logic array integrated circuit device includes a plurality of regions of programmable logic 20 disposed in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors 50, and each column has a plurality of adjacent vertical conductors 60. The regions 20 in a row are interspersed with groups of local conductors 40 which interconnect the adjacent regions (from both sides) and the associated horizontal and vertical conductors 50,60. The local conductors 40 can also be used for intra-region communication, as well as communication between adjacent regions 20. Secondary signals such as clocks and clears for the regions 20 can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by plural-stage progressively-finer selection.